1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
|
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/error.h"
/*
* basic read/write interface to mpc8xx Serial Peripheral Interface;
* used by devtouch.c and devspi.c
*/
typedef struct Ctlr Ctlr;
enum {
/* spi-specific BD flags */
BDContin= 1<<9, /* continuous mode */
RxeOV= 1<<1, /* overrun */
TxeUN= 1<<1, /* underflow */
BDme= 1<<0, /* multimaster error */
BDrxerr= RxeOV|BDme,
BDtxerr= TxeUN|BDme,
/* spmod */
MLoop= 1<<14, /* loopback mode */
MClockInv= 1<<13, /* inactive state of SPICLK is high */
MClockPhs= 1<<12, /* SPCLK starts toggling at beginning of transfer */
MDiv16= 1<<11, /* use BRGCLK/16 as input to SPI baud rate */
MRev= 1<<10, /* normal operation */
MMaster= 1<<9,
MSlave= 0<<9,
MEnable= 1<<8,
/* LEN, PS fields */
/* spcom */
STR= 1<<7, /* start transmit */
/* spie */
MME = 1<<5,
TXE = 1<<4,
BSY = 1<<2,
TXB = 1<<1,
RXB = 1<<0,
/* port B bits */
SPIMISO = IBIT(28), /* master mode input */
SPIMOSI = IBIT(29), /* master mode output */
SPICLK = IBIT(30),
/* maximum SPI I/O (can change) */
Bufsize = 64,
};
/*
* SPI software structures
*/
struct Ctlr {
Lock;
QLock io;
int init;
SPI* spi;
IOCparam* sp;
BD* rd;
BD* td;
int phase;
Rendez r;
char* txbuf;
char* rxbuf;
};
static Ctlr spictlr[1];
/* dcflush isn't needed if rxbuf and txbuf allocated in uncached IMMR memory */
#define DCFLUSH(a,n)
static void interrupt(Ureg*, void*);
/*
* called by the reset routine of any driver using the SPI
*/
void
spireset(void)
{
IMM *io;
SPI *spi;
IOCparam *sp;
CPMdev *cpm;
Ctlr *ctlr;
ctlr = spictlr;
if(ctlr->init)
return;
ctlr->init = 1;
cpm = cpmdev(CPspi);
spi = cpm->regs;
ctlr->spi = spi;
sp = cpm->param;
if(sp == nil){
print("SPI: can't allocate new parameter memory\n");
return;
}
ctlr->sp = sp;
if(ctlr->rxbuf == nil)
ctlr->rxbuf = cpmalloc(Bufsize, 2);
if(ctlr->txbuf == nil)
ctlr->txbuf = cpmalloc(Bufsize, 2);
if(ctlr->rd == nil){
ctlr->rd = bdalloc(1);
ctlr->rd->addr = PADDR(ctlr->rxbuf);
ctlr->rd->length = 0;
ctlr->rd->status = BDWrap;
}
if(ctlr->td == nil){
ctlr->td = bdalloc(1);
ctlr->td->addr = PADDR(ctlr->txbuf);
ctlr->td->length = 0;
ctlr->td->status = BDWrap|BDLast;
}
/* select port pins */
io = ioplock();
io->pbdir |= SPICLK | SPIMOSI | SPIMISO;
io->pbpar |= SPICLK | SPIMOSI | SPIMISO;
iopunlock();
/* explicitly initialise parameters, because InitRxTx can't be used (see i2c/spi relocation errata) */
sp = ctlr->sp;
sp->rbase = PADDR(ctlr->rd);
sp->tbase = PADDR(ctlr->td);
sp->rfcr = 0x18;
sp->tfcr = 0x18;
sp->mrblr = Bufsize;
sp->rstate = 0;
sp->rptr = 0;
sp->rbptr = sp->rbase;
sp->rcnt = 0;
sp->tstate = 0;
sp->tbptr = sp->tbase;
sp->tptr = 0;
sp->tcnt = 0;
eieio();
spi->spmode = MDiv16 | MRev | MMaster | ((8-1)<<4) | 1; /* 8 bit characters */
if(0)
spi->spmode |= MLoop; /* internal loop back mode for testing */
spi->spie = ~0; /* clear events */
eieio();
spi->spim = MME|TXE|BSY|TXB|RXB;
eieio();
spi->spmode |= MEnable;
intrenable(VectorCPIC+cpm->irq, interrupt, spictlr, BUSUNKNOWN, "spi");
}
enum {
Idling,
Waitval,
Readyval
};
static void
interrupt(Ureg*, void *arg)
{
int events;
Ctlr *ctlr;
SPI *spi;
ctlr = arg;
spi = ctlr->spi;
events = spi->spie;
eieio();
spi->spie = events;
if(events & (MME|BSY|TXE)){
print("SPI#%x\n", events);
if(ctlr->phase != Idling){
ctlr->phase = Idling;
wakeup(&ctlr->r);
}
}else if(events & RXB){
if(ctlr->phase == Waitval){
ctlr->phase = Readyval;
wakeup(&ctlr->r);
}
}
}
static int
done(void *a)
{
return ((Ctlr*)a)->phase != Waitval;
}
/*
* send `nout' bytes on SPI from `out' and read as many bytes of reply into buffer `in';
* return the number of bytes received, or -1 on error.
*/
long
spioutin(void *out, long nout, void *in)
{
Ctlr *ctlr;
int nb, p;
ctlr = spictlr;
if(nout > Bufsize)
return -1;
qlock(&ctlr->io);
if(waserror()){
qunlock(&ctlr->io);
return -1;
}
if(ctlr->phase != Idling)
sleep(&ctlr->r, done, ctlr);
memmove(ctlr->txbuf, out, nout);
DCFLUSH(ctlr->txbuf, Bufsize);
DCFLUSH(ctlr->rxbuf, Bufsize);
ilock(ctlr);
ctlr->phase = Waitval;
ctlr->td->length = nout;
ctlr->rd->status = BDEmpty|BDWrap|BDInt;
ctlr->td->status = BDReady|BDWrap|BDLast;
eieio();
ctlr->spi->spcom = STR;
eieio();
iunlock(ctlr);
sleep(&ctlr->r, done, ctlr);
nb = ctlr->rd->length;
if(nb > nout)
nb = nout; /* shouldn't happen */
p = ctlr->phase;
poperror();
qunlock(&ctlr->io);
if(p != Readyval)
return -1;
memmove(in, ctlr->rxbuf, nb);
return nb;
}
|
