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AgeCommit message (Expand)Author
2024-05-15Added a check to enable Thumb-2 floating point code to be treated differentlyDavid Boddie
2024-04-22Merge pull request #11 from dboddie/thumb2-compiler-changesCharles Forsyth
2024-04-22Merge pull request #9 from dboddie/add-data2textsCharles Forsyth
2023-11-16Fixed support for the status flag in some AND instructions.David Boddie
2023-11-16Added a definition for the temporary floating point register.David Boddie
2023-11-16Reassigned the temporary floating point register.David Boddie
2023-11-16Adapted code from 5l to simplify the FP comparison case.David Boddie
2023-11-16Used modified VFP instruction sequences from 5l.David Boddie
2023-11-16Unsuccessfully tried to implement reasonable sets of instructions.David Boddie
2023-11-16Made single and double FP register usage consistent.David Boddie
2023-11-16Adjusted transfers between doubles and register pairs.David Boddie
2023-11-16Fixed register encoding, or at least made our use of registers consistent.David Boddie
2023-11-16Added a note about the number of floating point registers.David Boddie
2023-11-16Enabled assembly of constant strings into the text segment.David Boddie
2023-11-16Imposed limitations on supported instruction encodings.David Boddie
2023-11-16Build the Thumb suite by default.David Boddie
2023-11-16Moved division and modulo operator support into the compiler.David Boddie
2023-11-16Added support for AND instruction variants.David Boddie
2023-11-16Tidied up the thumbopfp function and added a case for ACMPD.David Boddie
2023-11-16Brought the order of operations in line with the VFP instructions in 5l for e...David Boddie
2023-11-16Added support for more floating point operations.David Boddie
2023-11-16Added entries to the optab for combinations that occur when compiling bits of...David Boddie
2023-11-16Started trying to add missing instructions.David Boddie
2023-11-16Changed an entry in the opcode table to reflect the direction of conversion.David Boddie
2023-11-16Handled loads and stores using different base registers with slightly differe...David Boddie
2023-11-16Speculatively enable more FP instructions.David Boddie
2023-11-16Worked on converting ARM instructions to Thumb instructions for floating poin...David Boddie
2023-11-16Removed unused array entry.David Boddie
2023-11-16Renumbered FP opcodes and imported cases from the arm.c assembler.David Boddie
2023-11-16Prevented change to regular ARM mode.David Boddie
2023-11-16Added FP instructions from the optab.c file.David Boddie
2023-11-16Fixed typo.David Boddie
2023-11-16Update outlstring function in tc to match othersDavid Boddie
2023-11-16Added a variant of data2s that puts data in the text section.David Boddie
2021-09-30Update outlstring function in tc to match othersDavid Boddie
2021-09-30install tl as tl not 5lCharles Forsyth
2021-03-23update NOTICEs and other legal bits to reflect changes to Plan 9's licence an...Charles Forsyth
2021-03-11remove obsolete All rights reserved. fix email addressCharles Forsyth
2021-03-07Merged in utils-riscv (pull request #10)Richard Miller
2021-02-03Merged in Linux/spim (pull request #11)David Boddie
2021-01-01Renamed "mips" structure member to avoid reserved symbol conflictsPaul Boddie
2020-12-08il: align data segment between small and large varsRichard Miller
2020-12-08jc: fix opcode for vlong shiftsRichard Miller
2020-12-08jc: use MOVWU for unsigned int register loadRichard Miller
2020-11-09Merged in dboddie/inferno-os-git/fix-armv3 (pull request #6)David Boddie
2020-11-09Add toolchain for riscv (ia ic il) and riscv64 (ja jc jl)Richard Miller
2020-11-09Add riscv and riscv64 support to libmachRichard Miller
2020-07-18Fixed case 60 which used an ARMv4 instruction regardless of version.David Boddie
2018-12-21Merged in yk/inferno-os/AIX-power (pull request #17)Charles Forsyth
2017-07-15Reverted casts in asm.c, changing types in l.h to compensate.David Boddie
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