diff options
Diffstat (limited to 'lib/acid/power')
| -rw-r--r-- | lib/acid/power | 233 |
1 files changed, 233 insertions, 0 deletions
diff --git a/lib/acid/power b/lib/acid/power new file mode 100644 index 00000000..0691e243 --- /dev/null +++ b/lib/acid/power @@ -0,0 +1,233 @@ +// Power PC support + +defn acidinit() // Called after all the init modules are loaded +{ + bpl = {}; + bpid = -1; + bpfmt = 'X'; + nopstop = 0; + bplist = {}; + + srcpath = { + "./", + "/sys/src/libc/port/", + "/sys/src/libc/9sys/", + "/sys/src/libc/power/" + }; + + srcfiles = {}; // list of loaded files + srctext = {}; // the text of the files +} + +// defn stk() // trace +// { +// _stk(*PC, *SP, linkreg(0), 0); +// } + +// defn lstk() // trace with locals +// { +// _stk(*PC, *SP, linkreg(0), 1); +// } + +defn ustk(ur) +{ + complex Ureg ur; + _stk(ur.pc, ur.sp, 0, 0); +} + +defn lustk(ur) +{ + complex Ureg ur; + _stk(ur.pc, ur.sp, 0, 1); +} + +defn stk() +{ + ustk(0); +} + +defn lstk() +{ + lustk(0); +} + +defn kstk() +{ + local lab; + complex Proc proc; + lab = proc.sched; + complex Label lab; + _stk(lab.pc\X, lab.sp\X, 0, 0); +} + +defn lkstk() +{ + local lab; + complex Proc proc; + lab = proc.sched; + complex Label lab; + _stk(lab.pc\X, lab.sp\X, 0, 1); +} + +defn gpr() // print general purpose registers +{ + print("SP\t", *SP, " R2\t", *R2, " R3\t", *R3, "\n"); + print("R4\t", *R4, " R5\t", *R5, " R6\t", *R6, "\n"); + print("R7\t", *R7, " R8\t", *R8, " R9\t", *R9, "\n"); + print("R10\t", *R10, " R11\t", *R11, " R12\t", *R12, "\n"); + print("R13\t", *R13, " R14\t", *R14, " R15\t", *R15, "\n"); + print("R16\t", *R16, " R17\t", *R17, " R18\t", *R18, "\n"); + print("R19\t", *R19, " R20\t", *R20, " R21\t", *R21, "\n"); + print("R22\t", *R22, " R23\t", *R23, " R24\t", *R24, "\n"); + print("R25\t", *R25, " R26\t", *R26, " R27\t", *R27, "\n"); + print("R28\t", *R28, " R29\t", *R29, " R30\t", *R30, "\n"); + print("R31\t", *R31, "\n"); +} + +defn Fpr() +{ + fpr(); +} + +defn fpr() +{ + print("F0\t", *fmt(F0, 'G'), "\tF1\t", *fmt(F1, 'G'), "\n"); + print("F2\t", *fmt(F2, 'G'), "\tF3\t", *fmt(F3, 'G'), "\n"); + print("F4\t", *fmt(F4, 'G'), "\tF5\t", *fmt(F5, 'G'), "\n"); + print("F6\t", *fmt(F6, 'G'), "\tF7\t", *fmt(F7, 'G'), "\n"); + print("F8\t", *fmt(F8, 'G'), "\tF9\t", *fmt(F9, 'G'), "\n"); + print("F10\t", *fmt(F10, 'G'), "\tF11\t", *fmt(F11, 'G'), "\n"); + print("F12\t", *fmt(F12, 'G'), "\tF13\t", *fmt(F13, 'G'), "\n"); + print("F14\t", *fmt(F14, 'G'), "\tF15\t", *fmt(F15, 'G'), "\n"); + print("F16\t", *fmt(F16, 'G'), "\tF17\t", *fmt(F17, 'G'), "\n"); + print("F18\t", *fmt(F18, 'G'), "\tF19\t", *fmt(F19, 'G'), "\n"); + print("F20\t", *fmt(F20, 'G'), "\tF21\t", *fmt(F21, 'G'), "\n"); + print("F22\t", *fmt(F22, 'G'), "\tF23\t", *fmt(F23, 'G'), "\n"); + print("F24\t", *fmt(F24, 'G'), "\tF25\t", *fmt(F25, 'G'), "\n"); + print("F26\t", *fmt(F26, 'G'), "\tF27\t", *fmt(F27, 'G'), "\n"); + print("F28\t", *fmt(F28, 'G'), "\tF29\t", *fmt(F29, 'G'), "\n"); + print("F30\t", *fmt(F30, 'G'), "\tF31\t", *fmt(F31, 'G'), "\n"); +} + +defn spr() // print special processor registers +{ + local pc, link, cause; + + pc = *PC; + print("PC\t", pc, " ", fmt(pc, 'a'), " "); + pfl(pc); + + link = *R31; + print("SP\t", *SP, "\tLINK\t", link, " ", fmt(link, 'a'), " "); + pfl(link); + + cause = *CAUSE; + print("SRR1\t", *SRR1, "\tCAUSE\t", cause, " ", reason(cause), "\n"); + print("LR\t", *LR, "\tCR\t", *CR, "\n"); + + print("XER\t", *XER, "\tCTR\t", *CTR, "\n"); +} + +defn regs() // print all registers +{ + spr(); + gpr(); +} + + +defn linkreg(addr) +{ + return *LR; +} + +sizeofUreg = 160; +aggr Ureg +{ + 'U' 0 cause; + 'U' 4 status; + 'U' 8 pc; + 'U' 12 pad; + 'U' 16 lr; + 'U' 20 cr; + 'U' 24 xer; + 'U' 28 ctr; + 'U' 32 r0; + 'U' 36 sp; + 'U' 40 r2; + 'U' 44 r3; + 'U' 48 r4; + 'U' 52 r5; + 'U' 56 r6; + 'U' 60 r7; + 'U' 64 r8; + 'U' 68 r9; + 'U' 72 r10; + 'U' 76 r11; + 'U' 80 r12; + 'U' 84 r13; + 'U' 88 r14; + 'U' 92 r15; + 'U' 96 r16; + 'U' 100 r17; + 'U' 104 r18; + 'U' 108 r19; + 'U' 112 r20; + 'U' 116 r21; + 'U' 120 r22; + 'U' 124 r23; + 'U' 128 r24; + 'U' 132 r25; + 'U' 136 r26; + 'U' 140 r27; + 'U' 144 r28; + 'U' 148 r29; + 'U' 152 r30; + 'U' 156 r31; +}; + +defn +Ureg(addr) { + complex Ureg addr; + print(" cause ", addr.cause, "\n"); + print(" status ", addr.status, "\n"); + print(" pc ", addr.pc, "\n"); + print(" pad ", addr.pad, "\n"); + print(" lr ", addr.lr, "\n"); + print(" cr ", addr.cr, "\n"); + print(" xer ", addr.xer, "\n"); + print(" ctr ", addr.ctr, "\n"); + print(" r0 ", addr.r0, "\n"); + print(" sp ", addr.sp, "\n"); + print(" r2 ", addr.r2, "\n"); + print(" r3 ", addr.r3, "\n"); + print(" r4 ", addr.r4, "\n"); + print(" r5 ", addr.r5, "\n"); + print(" r6 ", addr.r6, "\n"); + print(" r7 ", addr.r7, "\n"); + print(" r8 ", addr.r8, "\n"); + print(" r9 ", addr.r9, "\n"); + print(" r10 ", addr.r10, "\n"); + print(" r11 ", addr.r11, "\n"); + print(" r12 ", addr.r12, "\n"); + print(" r13 ", addr.r13, "\n"); + print(" r14 ", addr.r14, "\n"); + print(" r15 ", addr.r15, "\n"); + print(" r16 ", addr.r16, "\n"); + print(" r17 ", addr.r17, "\n"); + print(" r18 ", addr.r18, "\n"); + print(" r19 ", addr.r19, "\n"); + print(" r20 ", addr.r20, "\n"); + print(" r21 ", addr.r21, "\n"); + print(" r22 ", addr.r22, "\n"); + print(" r23 ", addr.r23, "\n"); + print(" r24 ", addr.r24, "\n"); + print(" r25 ", addr.r25, "\n"); + print(" r26 ", addr.r26, "\n"); + print(" r27 ", addr.r27, "\n"); + print(" r28 ", addr.r28, "\n"); + print(" r29 ", addr.r29, "\n"); + print(" r30 ", addr.r30, "\n"); + print(" r31 ", addr.r31, "\n"); +}; + +print("/sys/lib/acid/power"); |