#ifndef __DD_STM32F769_CLOCKS_H__
#define __DD_STM32F769_CLOCKS_H__

#define STM32F769_CLOCK_CONFIG(reg, bit)                \
  (((STM32F769_RCC_ ## reg ## _OFFSET) << 6U) | (bit))

#define STM32F769_RCC_SYS_SET_OFFSET        0x80U

#define STM32F769_RCC_AHB1_SET_OFFSET       0x30U
#define STM32F769_RCC_AHB2_SET_OFFSET       0x34U
#define STM32F769_RCC_AHB3_SET_OFFSET       0x38U
#define STM32F769_RCC_APB1_SET_OFFSET       0x40U
#define STM32F769_RCC_APB2_SET_OFFSET       0x44U

#define STM32F769_CLOCK_SYS STM32F769_CLOCK_CONFIG(SYS_SET, 0)

#define STM32F769_CLOCK_TIM6 STM32F769_CLOCK_CONFIG(APB1_SET, 4U)

#define STM32F769_CLOCK_USART1 STM32F769_CLOCK_CONFIG(APB2_SET, 4U)
#define STM32F769_CLOCK_USART2 STM32F769_CLOCK_CONFIG(APB1_SET, 17U)
#define STM32F769_CLOCK_USART3 STM32F769_CLOCK_CONFIG(APB1_SET, 18U)
#define STM32F769_CLOCK_UART4 STM32F769_CLOCK_CONFIG(APB1_SET, 19U)
#define STM32F769_CLOCK_UART5 STM32F769_CLOCK_CONFIG(APB1_SET, 20U)
#define STM32F769_CLOCK_USART6 STM32F769_CLOCK_CONFIG(APB2_SET, 5U)
#define STM32F769_CLOCK_UART7 STM32F769_CLOCK_CONFIG(APB1_SET, 30U)
#define STM32F769_CLOCK_UART8 STM32F769_CLOCK_CONFIG(APB1_SET, 31U)

#define STM32F769_CLOCK_GPIOA STM32F769_CLOCK_CONFIG(AHB1_SET, 0U)
#define STM32F769_CLOCK_GPIOB STM32F769_CLOCK_CONFIG(AHB1_SET, 1U)
#define STM32F769_CLOCK_GPIOC STM32F769_CLOCK_CONFIG(AHB1_SET, 2U)
#define STM32F769_CLOCK_GPIOD STM32F769_CLOCK_CONFIG(AHB1_SET, 3U)
#define STM32F769_CLOCK_GPIOE STM32F769_CLOCK_CONFIG(AHB1_SET, 4U)
#define STM32F769_CLOCK_GPIOF STM32F769_CLOCK_CONFIG(AHB1_SET, 5U)
#define STM32F769_CLOCK_GPIOG STM32F769_CLOCK_CONFIG(AHB1_SET, 6U)
#define STM32F769_CLOCK_GPIOH STM32F769_CLOCK_CONFIG(AHB1_SET, 7U)
#define STM32F769_CLOCK_GPIOI STM32F769_CLOCK_CONFIG(AHB1_SET, 8U)
#define STM32F769_CLOCK_GPIOJ STM32F769_CLOCK_CONFIG(AHB1_SET, 9U)
#define STM32F769_CLOCK_GPIOK STM32F769_CLOCK_CONFIG(AHB1_SET, 10U)

#define STM32F769_CLOCK_PWR STM32F769_CLOCK_CONFIG(APB1_SET, 28U)

#endif /* __DD_STM32F769_CLOCKS_H__ */