From 46439007cf417cbd9ac8049bb4122c890097a0fa Mon Sep 17 00:00:00 2001
From: "Charles.Forsyth" <devnull@localhost>
Date: Fri, 22 Dec 2006 20:52:35 +0000
Subject: 20060303-partial

---
 man/8/fpgaload | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 man/8/fpgaload

(limited to 'man/8/fpgaload')

diff --git a/man/8/fpgaload b/man/8/fpgaload
new file mode 100644
index 00000000..c6cf440a
--- /dev/null
+++ b/man/8/fpgaload
@@ -0,0 +1,24 @@
+.TH FPGALOAD 8
+.SH NAME
+fpgaload \- configure FPGA
+.SH SYNOPSIS
+.B auxi/fpgaload
+[
+.BI -c " clk"
+]
+.I file.rbf
+.SH DESCRIPTION
+.I Fpgaload
+configures the directly-attached Altera Flex6000 FPGA on the Bright Star Engineering ip-Engine.
+It enables the FPGA and output of the external system clocks, then loads the FPGA with the contents of
+.IR file.rbf
+which should be in the `raw binary format' produced for example by the Altera tools.
+After successful configuration, the BCLK is set to
+.I clk
+MHz;
+.I clk
+must be a divisor of the ip-Engine's system clock (currently 48 MHz).
+.SH SOURCE
+.B /appl/cmd/auxi/fpgaload.b
+.SH SEE ALSO
+.IR fpga (3)
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