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-rw-r--r--os/Makefile93
-rw-r--r--os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c12
-rw-r--r--os/arch/aarch32/armv7e_m/stm32f769/init.c120
-rw-r--r--os/arch/aarch32/armv7e_m/stm32f769/sys_io.h10
-rw-r--r--os/config.h2
-rw-r--r--os/drivers/clock/stm32f769_clock_control.c464
-rw-r--r--os/drivers/clock/stm32f769_clock_control.h1
-rw-r--r--os/drivers/clock/stm32f769_clocks.h4
-rw-r--r--os/drivers/clock/stm32f769_rcc.h4
-rw-r--r--os/drivers/gpio/stm32f769_gpio.c243
-rw-r--r--os/drivers/gpio/stm32f769_gpio.h2
-rw-r--r--os/drivers/memory/stm32f7_mpu.c2
-rw-r--r--os/drivers/pinctrl/stm32f769_pinctrl.c70
-rw-r--r--os/drivers/pinctrl/stm32f769_pinctrl.h48
-rw-r--r--os/drivers/uart/stm32f7_uart.c21
15 files changed, 837 insertions, 259 deletions
diff --git a/os/Makefile b/os/Makefile
new file mode 100644
index 00000000..3ef6135d
--- /dev/null
+++ b/os/Makefile
@@ -0,0 +1,93 @@
+DEBUG = 1
+REVISION = $(shell git rev-list HEAD --count)
+DIRTY = $(shell git diff-index --quiet HEAD; echo $$?)
+ifeq ($(DIRTY),1)
+ SUFFIX = "-rc"
+else
+ SUFFIX = ""
+endif
+
+PROJECT = test
+TARGET = $(PROJECT).elf
+CROSS_COMPILE=~/zephyr-sdk-0.17.1/arm-zephyr-eabi/bin/arm-zephyr-eabi-
+CC = $(CROSS_COMPILE)gcc
+LD = $(CROSS_COMPILE)gcc
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = $(CROSS_COMPILE)objcopy
+OBJDUMP = $(CROSS_COMPILE)objdump
+SIZE = $(CROSS_COMPILE)size
+
+SOURCES = main.c
+SOURCES+= arch/aarch32/armv7e_m/stm32f769/init.c
+SOURCES+= arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c
+SOURCES+= drivers/clock/stm32f769_clock_control.c
+SOURCES+= drivers/pinctrl/stm32f769_pinctrl.c
+SOURCES+= drivers/gpio/stm32f769_gpio.c
+SOURCES+= drivers/memory/stm32f7_mpu.c
+SOURCES+= drivers/uart/stm32f7_uart.c
+
+LDFLAGS = -nostartfiles -nostdlib -nodefaultlibs -lgcc
+LDFLAGS+= -Wl,-Map=$(PROJECT).map,--gc-sections
+LDFLAGS+= -Tarch/aarch32/armv7e_m/stm32f769/link.ld -mfloat-abi=hard -mfpu=fpv5-sp-d16 -march=armv8-m.main+dsp
+#LDFLAGS += -flto
+#LDFLAGS += -Tld/spifi.ld -march=rv32imc_zicsr_zifencei
+
+CFLAGS = -Wall -Wextra -std=gnu99 -funsigned-char -funsigned-bitfields
+CFLAGS+= -mfloat-abi=hard -mfpu=fpv5-sp-d16 -march=armv8-m.main+dsp
+ifneq ($(DEBUG),1)
+#CFLAGS += -flto -O2
+else
+#CFLAGS += -flto -O2
+CFLAGS+= -ggdb3
+endif
+CFLAGS+= -fshort-enums -ffunction-sections -fdata-sections -fno-delete-null-pointer-checks
+CFLAGS+= -fno-builtin
+CFLAGS+= -I./
+
+# CFLAGS += -DEN_I2C1
+# CFLAGS += -DEN_I2C0
+# CFLAGS += -DEN_USART1
+# CFLAGS += -DEN_EEPROM
+#CFLAGS += -DIRQ_TRACE
+#CFLAGS += -DEN_TSENS
+#CFLAGS += -DCOMPACT
+
+ASSOURCES = arch/aarch32/armv7e_m/stm32f7/startup_stm32f769xx.s
+
+ASFLAGS = $(COMMON)
+ASFLAGS += $(CFLAGS)
+ASFLAGS += -x assembler-with-cpp
+
+OBJECTS = $(SOURCES:.c=.o)
+ASOBJECTS = $(ASSOURCES:.s=.o)
+
+DEPS=$(patsubst %.o, %.o.d, $(notdir $(OBJECTS)))
+DEPS+=$(patsubst %.o, %.o.d, $(notdir $(ASOBJECTS)))
+
+all: $(TARGET) $(PROJECT).bin $(PROJECT).lss size
+
+$(PROJECT).bin: $(TARGET)
+ $(OBJCOPY) -O binary $< $@
+ cp $(PROJECT).bin $(PROJECT)-$(REVISION)-$(BOARD)$(SUFFIX).bin
+
+$(PROJECT).lss: $(TARGET)
+ $(OBJDUMP) -h -S $< > $@
+
+$(TARGET): $(OBJECTS) $(ASOBJECTS)
+ $(LD) $(LDFLAGS) $(OBJECTS) $(ASOBJECTS) -o $@
+
+$(OBJECTS): %.o: %.c
+ $(CC) $(CFLAGS) -c $< -o $@
+
+$(ASOBJECTS): %.o: %.s
+ $(CC) $(ASFLAGS) -c $< -o $@
+
+.PHONY: size
+size: ${TARGET}
+ @echo
+ @$(SIZE) ${TARGET}
+
+## Clean target
+.PHONY: clean
+clean:
+ rm $(OBJECTS) $(ASOBJECTS) $(PROJECT).bin $(PROJECT).elf $(PROJECT).map $(PROJECT).lss $(DEPS) *.bin *.elf *.map *.lss
diff --git a/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c b/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c
index bf363777..695a9271 100644
--- a/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c
+++ b/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c
@@ -47,10 +47,6 @@
#include <config.h>
#include "stm32f7xx.h"
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@@ -122,7 +118,7 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
- uint32_t SystemCoreClock = 16000000;
+ uint32_t SystemCoreClock = HSI_VALUE;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
@@ -211,7 +207,7 @@ void SystemCoreClockUpdate(void)
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
+ SystemCoreClock = CONFIG_BOARD_HSE_CLK;
break;
case 0x08: /* PLL used as system clock source */
@@ -224,7 +220,7 @@ void SystemCoreClockUpdate(void)
if (pllsource != 0)
{
/* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ pllvco = (CONFIG_BOARD_HSE_CLK / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
@@ -233,7 +229,7 @@ void SystemCoreClockUpdate(void)
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
+ SystemCoreClock = pllvco / pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
diff --git a/os/arch/aarch32/armv7e_m/stm32f769/init.c b/os/arch/aarch32/armv7e_m/stm32f769/init.c
index 571e36e4..bda2c154 100644
--- a/os/arch/aarch32/armv7e_m/stm32f769/init.c
+++ b/os/arch/aarch32/armv7e_m/stm32f769/init.c
@@ -6,22 +6,18 @@
#include <drivers/memory/stm32f7_mpu.h>
#include <drivers/clock/stm32f769_clocks.h>
#include <drivers/clock/stm32f769_clock_control.h>
+#include <drivers/pinctrl/stm32f769_pinctrl.h>
#include <drivers/uart/stm32f7_uart.h>
#include <drivers/uart/uart.h>
+#include <drivers/gpio/gpio.h>
+#include <drivers/gpio/stm32f769_gpio.h>
#include "cortex.h"
struct device mpu;
struct device clkctrl;
struct device usart1;
-
-struct rcc_clk_init {
- uint32_t ClockType;
- uint32_t SYSCLKSource;
- uint32_t AHBCLKDivider;
- uint32_t APB1CLKDivider;
- uint32_t APB2CLKDivider;
-};
+struct device gpioj;
extern volatile uint64_t uptime_ctr;
@@ -40,62 +36,52 @@ static void __cpu_cache_enable(void)
SCB_EnableDCache();
}
-#define __FLASH_ART_ENABLE() sys_set_bit(FLASH->ACR, FLASH_ACR_ARTEN)
-#define __FLASH_PREFETCH_BUFFER_ENABLE() sys_set_bit(FLASH->ACR, FLASH_ACR_PRFTEN)
-#define TICK_INT_PRIORITY 0x0FU
-
-static void __nvic_setpriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+void WWDG_IRQHandler(void)
{
- uint32_t prioritygroup = 0x00;
- prioritygroup = NVIC_GetPriorityGrouping();
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ while (1) {
+ }
}
-static void __rcc_get_clock_config(struct rcc_clk_init *clkinit, uint32_t *flash_latency)
+void NMI_Handler(void)
{
- /* Set all possible values for the Clock type parameter --------------------*/
- clkinit->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
- clkinit->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- clkinit->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- clkinit->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
- clkinit->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *flash_latency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
}
-
-static int __init_tick (uint32_t TickPriority)
+void HardFault_Handler(void)
{
- struct rcc_clk_init clkconfig;
- //uint32_t uwTimclock, uwAPB1Prescaler = 0U;
- uint32_t flash_latency;
-
- /*Configure the TIM6 IRQ priority */
- __nvic_setpriority(SysTick_IRQn, TickPriority, 0U);
+ while (1)
+ {
+ }
+}
- /* Enable the TIM6 global Interrupt */
- NVIC_EnableIRQ(SysTick_IRQn);
+void MemManage_Handler(void)
+{
+ while (1)
+ {
+ }
+}
- /* Get clock configuration */
- __rcc_get_clock_config(&clkconfig, &flash_latency);
+void BusFault_Handler(void)
+{
+ while (1)
+ {
+ }
+}
- uint32_t sys_rate = 0;
- stm32f769_clock_control_get_rate(STM32F769_RCC_SYS_SET_OFFSET, &sys_rate);
+void UsageFault_Handler(void)
+{
+ while (1)
+ {
+ }
+}
- sys_write32(((sys_rate / 1000) - 1) & SysTick_LOAD_RELOAD_Msk, SysTick->LOAD);
- sys_clear_bits(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);
+#define __FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
+#define __FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
- /* Return function status */
- return 0;
+static void __nvic_setpriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00;
+ prioritygroup = NVIC_GetPriorityGrouping();
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
void arch_init(void) {
@@ -112,10 +98,13 @@ void arch_init(void) {
#endif /* PREFETCH_ENABLE */
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- __init_tick(TICK_INT_PRIORITY);
+ stm32f769_init_tick();
- stm32f769_clock_control_init(&clkctrl);
+ if (stm32f769_clock_control_init(&clkctrl) < 0) {
+ while (1) {}
+ }
+ stm32f769_clock_control_on(STM32F769_CLOCK_GPIOA);
stm32f769_clock_control_on(STM32F769_CLOCK_USART1);
struct uart_data u1_data;
@@ -128,12 +117,33 @@ void arch_init(void) {
usart1.devptr = USART1;
usart1.data = &u1_data;
- stm32f7_uart_init(&usart1);
+ stm32f769_pinctrl_configure_pin(STM32F769_PINMUX_AF(STM32F769_PORTA, 9, AF7));
+ stm32f769_pinctrl_configure_pin(STM32F769_PINMUX_AF(STM32F769_PORTA, 10, AF7));
+
+ if (stm32f7_uart_init(&usart1) < 0) {
+ while (1) {
+ }
+ }
+
stm32f7_uart_tx(&usart1, "Start\r\n");
+ gpioj.devptr = GPIOJ;
+ stm32f769_gpio_init(&gpioj);
+ stm32f769_gpio_configure(&gpioj, 13, GPIO_OUTPUT);
+ int stat = 0;
+ uint32_t sys_rate = 0;
+
while (1) {
+ if (stat) {
+ stm32f769_gpio_write(&gpioj, 13, stat);
+ stat = 0;
+ } else {
+ stm32f769_gpio_write(&gpioj, 13, stat);
+ stat = 1;
+ }
stm32f7_uart_tx(&usart1, "Test\r\n");
wait(1000);
+ stm32f769_clock_control_get_rate(STM32F769_CLOCK_SYS, &sys_rate);
}
return;
}
diff --git a/os/arch/aarch32/armv7e_m/stm32f769/sys_io.h b/os/arch/aarch32/armv7e_m/stm32f769/sys_io.h
index 9f70d641..77a33dd1 100644
--- a/os/arch/aarch32/armv7e_m/stm32f769/sys_io.h
+++ b/os/arch/aarch32/armv7e_m/stm32f769/sys_io.h
@@ -10,6 +10,14 @@
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
#endif
+#define SET_BIT(r, b) (r |= (b))
+#define CLEAR_BIT(r, b) (r &= ~(b))
+#define READ_BIT(r, b) ((r) & (b))
+#define CLEAR_REG(r) ((r) = (0x0))
+#define WRITE_REG(r, v) ((r) = (v))
+#define READ_REG(r) ((r))
+#define MODIFY_REG(r, clear_mask, set_mask) WRITE_REG((r), (((READ_REG(r)) & (~(clear_mask))) | (set_mask)))
+
static inline uint8_t sys_read8(uint32_t addr)
{
return *(volatile uint8_t *)addr;
@@ -66,7 +74,7 @@ static inline void sys_clear_bit(uint32_t addr, unsigned int bit)
static inline int sys_test_bit(uint32_t addr, unsigned int bit)
{
- uint32_t temp = *(volatile uint32_t *)addr;
+ volatile uint32_t temp = *(volatile uint32_t *)addr;
return temp & (1 << bit);
}
diff --git a/os/config.h b/os/config.h
index 46961a62..1b973fbd 100644
--- a/os/config.h
+++ b/os/config.h
@@ -3,7 +3,7 @@
#define CONFIG_BOARD_HSE_CLK 25000000U
#define CONFIG_BOARD_HSE_BYP 0
-#define CONFIG_BOARD_SYS_CLK 100000000U
+#define CONFIG_BOARD_SYS_CLK 216000000U
#define CONFIG_ARCH_AARCH32 1
#define CONFIG_ARCH_SUB_ARMV7E_M 1
diff --git a/os/drivers/clock/stm32f769_clock_control.c b/os/drivers/clock/stm32f769_clock_control.c
index 31cc8f1a..e9b6bf2a 100644
--- a/os/drivers/clock/stm32f769_clock_control.c
+++ b/os/drivers/clock/stm32f769_clock_control.c
@@ -8,8 +8,28 @@
#include "errno.h"
#include "stm32f769_clocks.h"
+#define TICK_INT_PRIORITY 0x0FU
+
#define STM32F769_CLOCK_ID_OFFSET(id) (((id) >> 6U) & 0xFFU)
-#define STM32F769_CLOCK_ID_BIT(id) ((id)&0x1FU)
+#define STM32F769_CLOCK_ID_BIT(id) (id & 0x1FU)
+
+#define HSI_VALUE 16000000
+
+enum CLK_SOURCE {
+ CS_UNKNOWN = 0,
+ CS_HSI,
+ CS_HSE,
+ CS_PLL_HSI,
+ CS_PLL_HSE,
+};
+
+struct rcc_clk_init {
+ uint32_t ClockType;
+ uint32_t SYSCLKSource;
+ uint32_t AHBCLKDivider;
+ uint32_t APB1CLKDivider;
+ uint32_t APB2CLKDivider;
+};
volatile uint64_t uptime_ctr;
@@ -18,10 +38,12 @@ void SysTick_Handler(void) {
}
int stm32f769_clock_control_on(uint16_t id) {
+ uint32_t addr = RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id);
+ uint32_t bit = STM32F769_CLOCK_ID_BIT(id);
sys_set_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id),
STM32F769_CLOCK_ID_BIT(id));
- int ret = sys_test_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id),
- STM32F769_CLOCK_ID_BIT(id));
+ volatile int ret = sys_test_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id),
+ STM32F769_CLOCK_ID_BIT(id));
(void)ret;
return 0;
}
@@ -60,7 +82,7 @@ static uint32_t __get_ahb_div(uint32_t val) {
}
}
-static uint32_t __get_apb_div(uint32_t val) {
+static uint32_t __get_apb1_div(uint32_t val) {
switch (val) {
case RCC_CFGR_PPRE1_DIV2:
return 2;
@@ -76,17 +98,160 @@ static uint32_t __get_apb_div(uint32_t val) {
}
}
+static uint32_t __get_apb2_div(uint32_t val) {
+ switch (val) {
+ case RCC_CFGR_PPRE2_DIV2:
+ return 2;
+ case RCC_CFGR_PPRE2_DIV4:
+ return 4;
+ case RCC_CFGR_PPRE2_DIV8:
+ return 8;
+ case RCC_CFGR_PPRE2_DIV16:
+ return 16;
+ case RCC_CFGR_PPRE2_DIV1:
+ default:
+ return 1;
+ }
+}
+
+uint32_t __get_sysclk(void)
+{
+ uint64_t plln = 0;
+ uint32_t pllm = 0, pllvco = 0, pllp = 0;
+ uint32_t clk = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ {
+ clk = HSI_VALUE;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ {
+ clk = CONFIG_BOARD_HSE_CLK;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ plln = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (uint32_t)((((uint64_t) CONFIG_BOARD_HSE_CLK * ((uint64_t)plln))) / (uint64_t)pllm);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ }
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
+
+ clk = pllvco / pllp;
+ break;
+ }
+ default:
+ {
+ clk = HSI_VALUE;
+ break;
+ }
+ }
+ return clk;
+}
+
+#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
+#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
+#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
+#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY
+#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
+#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY
+
+static int __enable_overdrive(void)
+{
+ uint32_t tickstart = 0;
+
+ stm32f769_clock_control_on(STM32F769_CLOCK_PWR);
+
+ __HAL_PWR_OVERDRIVE_ENABLE();
+ tickstart = uptime_ctr;
+
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+ {
+ if((uptime_ctr - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ {
+ return -1;
+ }
+ }
+
+ __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
+ tickstart = uptime_ctr;
+
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+ {
+ if((uptime_ctr - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ {
+ return -1;
+ }
+ }
+ return 0;
+}
+
+/* HAL_StatusTypeDef __disable_overdrive(void) */
+/* { */
+/* uint32_t tickstart = 0; */
+
+/* __HAL_RCC_PWR_CLK_ENABLE(); */
+
+/* /\* Disable the Over-drive switch *\/ */
+/* __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); */
+
+/* /\* Get tick *\/ */
+/* tickstart = HAL_GetTick(); */
+
+/* while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) */
+/* { */
+/* if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) */
+/* { */
+/* return HAL_TIMEOUT; */
+/* } */
+/* } */
+
+/* /\* Disable the Over-drive *\/ */
+/* __HAL_PWR_OVERDRIVE_DISABLE(); */
+
+/* /\* Get tick *\/ */
+/* tickstart = HAL_GetTick(); */
+
+/* while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) */
+/* { */
+/* if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) */
+/* { */
+/* return HAL_TIMEOUT; */
+/* } */
+/* } */
+
+/* return HAL_OK; */
+/* } */
+
int stm32f769_clock_control_get_rate(uint16_t id, uint32_t *rate)
{
uint32_t clk_offt = STM32F769_CLOCK_ID_OFFSET(id);
uint32_t ahb_div = __get_ahb_div(RCC->CFGR & RCC_CFGR_HPRE_Msk);
- uint32_t apb1_div = __get_apb_div(RCC->CFGR & RCC_CFGR_PPRE1_Msk);
- uint32_t apb2_div = __get_apb_div(RCC->CFGR & RCC_CFGR_PPRE2_Msk);
- uint32_t ahb_rate = CONFIG_BOARD_SYS_CLK / ahb_div;
+ uint32_t apb1_div = __get_apb1_div(RCC->CFGR & RCC_CFGR_PPRE1_Msk);
+ uint32_t apb2_div = __get_apb2_div(RCC->CFGR & RCC_CFGR_PPRE2_Msk);
+ uint32_t ahb_rate = __get_sysclk() / ahb_div;
switch (clk_offt) {
case STM32F769_RCC_SYS_SET_OFFSET:
- *rate = CONFIG_BOARD_SYS_CLK;
+ *rate = __get_sysclk();
break;
case STM32F769_RCC_AHB1_SET_OFFSET:
*rate = ahb_rate;
@@ -122,11 +287,169 @@ int stm32f769_clock_control_get_rate(uint16_t id, uint32_t *rate)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
//#define PLL_TIMEOUT_VALUE 2
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
+
+static int __deinit_clk(void)
+{
+ uint32_t tickstart;
+
+ tickstart = uptime_ctr;
+
+ /* Set HSION bit to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0)
+ {
+ if ((uptime_ctr - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Set HSITRIM[4:0] bits to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+ /* Get Start Tick */
+ tickstart = uptime_ctr;
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Wait till clock switch is ready */
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0)
+ {
+ if ((uptime_ctr - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = uptime_ctr;
+
+ /* Clear HSEON, HSEBYP and CSSON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+ /* Wait till HSE is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0)
+ {
+ if ((uptime_ctr - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = uptime_ctr;
+
+ /* Clear PLLON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0)
+ {
+ if ((uptime_ctr - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = uptime_ctr;
+
+ /* Reset PLLI2SON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+ /* Wait till PLLI2S is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != 0)
+ {
+ if ((uptime_ctr - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = uptime_ctr;
+
+ /* Reset PLLSAI bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+
+ /* Wait till PLLSAI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != 0)
+ {
+ if ((uptime_ctr - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U;
+
+ /* Reset PLLI2SCFGR register to default value */
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+
+ /* Reset PLLSAICFGR register to default value */
+ RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U;
+
+ /* Disable all interrupts */
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
+
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ return stm32f769_init_tick();
+}
int stm32f769_clock_control_init(struct device *dev)
{
uint32_t tickstart;
- uint32_t pll_config;
+ enum CLK_SOURCE cs = CS_UNKNOWN;
+ int ret = 0;
+
+ uint32_t clk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
+ uint32_t pllcfgr = READ_REG(RCC->PLLCFGR);
+ uint32_t rcccr = READ_REG(RCC->CR);
+
+ switch (clk_source) {
+ case RCC_SYSCLKSOURCE_STATUS_HSE:
+ cs = CS_HSE;
+ break;
+ case RCC_SYSCLKSOURCE_STATUS_HSI:
+ cs = CS_HSI;
+ break;
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK:
+ if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE) {
+ cs = CS_PLL_HSE;
+ } else if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI) {
+ cs = CS_PLL_HSI;
+ } else {
+ while (1) {};
+ }
+ break;
+ default:
+ while (1) {};
+ break;
+ }
+
+ ret = __deinit_clk();
+ if (ret != 0) {
+ while (1) {};
+ }
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) {
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0)) {// && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) {
@@ -136,10 +459,10 @@ int stm32f769_clock_control_init(struct device *dev)
#if defined(CONFIG_BOARD_HSE_CLK)
#if CONFIG_BOARD_HSE_BYP == 1
- sys_set_bit(RCC->CR, RCC_CR_HSEBYP);
- sys_set_bit(RCC->CR, RCC_CR_HSEON);
+ RCC->CR |= RCC_CR_HSEBYP;
+ RCC->CR |= RCC_CR_HSEON;
#else
- sys_set_bit(RCC->CR, RCC_CR_HSEON);
+ RCC->CR |= RCC_CR_HSEON;
#endif
/* Get Start Tick*/
tickstart = uptime_ctr;
@@ -185,9 +508,126 @@ int stm32f769_clock_control_init(struct device *dev)
}
}
}
+
+ if (__enable_overdrive() != 0) {
+ while (1) {};
+ }
+
+ if (FLASH_ACR_LATENCY_7WS > __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLASH_ACR_LATENCY_7WS);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (__HAL_FLASH_GET_LATENCY() != FLASH_ACR_LATENCY_7WS)
+ {
+ while (1) {};
+ return -1;
+ }
+ }
+
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
+
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0)
+ {
+ while (1) {};
+ return -1;
+ }
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_PLLCLK);
+
+ /* Get Start Tick*/
+ tickstart = uptime_ctr;
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_SYSCLKSOURCE_PLLCLK << RCC_CFGR_SWS_Pos))
+ {
+ if ((uptime_ctr - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ while (1) {};
+ return -1;
+ }
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (FLASH_ACR_LATENCY_7WS < __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLASH_ACR_LATENCY_7WS);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (__HAL_FLASH_GET_LATENCY() != FLASH_ACR_LATENCY_7WS)
+ {
+ return -1;
+ }
+ }
+
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV4);
+
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_HCLK_DIV2) << 3));
+
+ SystemCoreClock = __get_sysclk() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
+
+ stm32f769_init_tick();
+ return 0;
+}
+
+
+static void __rcc_get_clock_config(struct rcc_clk_init *clkinit, uint32_t *flash_latency)
+{
+ /* Set all possible values for the Clock type parameter --------------------*/
+ clkinit->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ clkinit->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ clkinit->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ clkinit->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ clkinit->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *flash_latency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+int stm32f769_init_tick(void)
+{
+ uint32_t TickPriority = TICK_INT_PRIORITY;
+ struct rcc_clk_init clkconfig;
+ uint32_t flash_latency;
+
+ uint32_t prioritygroup = 0x00;
+ prioritygroup = NVIC_GetPriorityGrouping();
+ NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, TickPriority, 0));
+ //__nvic_setpriority(SysTick_IRQn, TickPriority, 0U);
+
+ /* Enable the TIM6 global Interrupt */
+ NVIC_EnableIRQ(SysTick_IRQn);
+
+ /* Get clock configuration */
+ __rcc_get_clock_config(&clkconfig, &flash_latency);
+
+ uint32_t ahb1_rate = 0;
+ stm32f769_clock_control_get_rate(STM32F769_CLOCK_GPIOA, &ahb1_rate);
+ uint32_t sys_rate = 0;
+ stm32f769_clock_control_get_rate(STM32F769_CLOCK_SYS, &sys_rate);
+
+ MODIFY_REG(SysTick->LOAD, SysTick_LOAD_RELOAD_Msk, ((ahb1_rate) / 1000) - 1);
+ CLEAR_BIT(SysTick->VAL, SysTick_VAL_CURRENT_Msk);
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);
+
+ /* Return function status */
return 0;
}
+
/* static enum clock_control_status */
/* clock_control_mik32_get_status(uint16_t id) */
/* { */
diff --git a/os/drivers/clock/stm32f769_clock_control.h b/os/drivers/clock/stm32f769_clock_control.h
index 0b272bde..23cfb906 100644
--- a/os/drivers/clock/stm32f769_clock_control.h
+++ b/os/drivers/clock/stm32f769_clock_control.h
@@ -8,5 +8,6 @@ int stm32f769_clock_control_on(uint16_t id);
int stm32f769_clock_control_off(uint16_t id);
int stm32f769_clock_control_get_rate(uint16_t id, uint32_t *rate);
int stm32f769_clock_control_init(struct device *dev);
+int stm32f769_init_tick (void);
#endif/*__STM32F769_CLOCK_CONTROL_H__*/
diff --git a/os/drivers/clock/stm32f769_clocks.h b/os/drivers/clock/stm32f769_clocks.h
index 4617a9be..b65c2bd5 100644
--- a/os/drivers/clock/stm32f769_clocks.h
+++ b/os/drivers/clock/stm32f769_clocks.h
@@ -12,6 +12,8 @@
#define STM32F769_RCC_APB1_SET_OFFSET 0x40U
#define STM32F769_RCC_APB2_SET_OFFSET 0x44U
+#define STM32F769_CLOCK_SYS STM32F769_CLOCK_CONFIG(SYS_SET, 0)
+
#define STM32F769_CLOCK_TIM6 STM32F769_CLOCK_CONFIG(APB1_SET, 4U)
#define STM32F769_CLOCK_USART1 STM32F769_CLOCK_CONFIG(APB2_SET, 4U)
@@ -35,4 +37,6 @@
#define STM32F769_CLOCK_GPIOJ STM32F769_CLOCK_CONFIG(AHB1_SET, 9U)
#define STM32F769_CLOCK_GPIOK STM32F769_CLOCK_CONFIG(AHB1_SET, 10U)
+#define STM32F769_CLOCK_PWR STM32F769_CLOCK_CONFIG(APB1_SET, 28U)
+
#endif /* __DD_STM32F769_CLOCKS_H__ */
diff --git a/os/drivers/clock/stm32f769_rcc.h b/os/drivers/clock/stm32f769_rcc.h
index 34cfd259..21e4f419 100644
--- a/os/drivers/clock/stm32f769_rcc.h
+++ b/os/drivers/clock/stm32f769_rcc.h
@@ -880,8 +880,8 @@ typedef struct
* @note The main PLL can not be disabled if it is used as system clock source
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
*/
-#define __HAL_RCC_PLL_ENABLE() sys_set_bit(RCC->CR, RCC_CR_PLLON)
-#define __HAL_RCC_PLL_DISABLE() sys_clear_bit(RCC->CR, RCC_CR_PLLON)
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
/** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled.
diff --git a/os/drivers/gpio/stm32f769_gpio.c b/os/drivers/gpio/stm32f769_gpio.c
index 250615b2..ce2561ae 100644
--- a/os/drivers/gpio/stm32f769_gpio.c
+++ b/os/drivers/gpio/stm32f769_gpio.c
@@ -1,5 +1,12 @@
-#include "gpio.h"
#include <arch/sys_io.h>
+#include <arch/aarch32/armv7e_m/stm32f7/stm32f769xx.h>
+#include <drivers/pinctrl/stm32f769_pinctrl.h>
+#include <drivers/clock/stm32f769_clocks.h>
+#include <drivers/clock/stm32f769_clock_control.h>
+
+#include <stddef.h>
+
+#include "gpio.h"
/* #include "memory_map.h" */
/* #include "soc_gpio.h" */
/* #include "soc.h" */
@@ -8,213 +15,219 @@
int stm32f769_gpio_configure_analog(struct device *dev, uint32_t pin, uint32_t flags)
{
-// const struct gpio_stm32f769_config *config = port->config;
- uint32_t port_idx = STM32F769_PORT_GET(pin);
+// const struct gpio_stm32f769_config *config = port->config;
GPIO_TypeDef *p = NULL;
if (dev == NULL) {
+ uint32_t port_idx = STM32F769_PORT_GET(pin);
p = stm32f769_get_port(port_idx);
} else {
p = dev->devptr;
}
- uint32_t moder = sys_read32(p->MODER);
- uint32_t ospeedr = sys_read32(p->OSPEEDR);
- uint32_t pupdr = sys_read32(p->PUPDR);
- uint32_t otyper = sys_read32(p->OTYPER);
+ uint32_t moder = READ_REG(p->MODER);
+ uint32_t ospeedr = READ_REG(p->OSPEEDR);
+ uint32_t pupdr = READ_REG(p->PUPDR);
+ uint32_t otyper = READ_REG(p->OTYPER);
+
+ uint32_t pin_num = pin & 0xf;
- moder |= ((0x3) << (pin * 2));
- sys_write32(moder, p->MODER);
+ moder |= ((0x3) << (pin_num * 2));
+ WRITE_REG(p->MODER, moder);
// Low speed
- ospeedr &= ~((0x3) << (pin * 2));
- sys_write32(ospeedr, p->OSPEEDR);
+ ospeedr &= ~((0x3) << (pin_num * 2));
+ WRITE_REG(p->OSPEEDR, ospeedr);
if ((flags & GPIO_OPEN_DRAIN) != 0U) {
- otyper |= (1 << pin);
+ otyper |= (1 << pin_num);
} else {
- otyper &= ~(1 << pin);
+ otyper &= ~(1 << pin_num);
+ }
+ WRITE_REG(p->OTYPER, otyper);
+
+ if ((flags & GPIO_PULL_UP) != 0U) {
+ pupdr &= ~(0x3 << (pin_num * 2));
+ pupdr |= (0x1 << (pin_num * 2));
+ } else if ((flags & GPIO_PULL_DOWN) != 0U) {
+ pupdr &= ~(0x3 << (pin_num * 2));
+ pupdr |= (0x2 << (pin_num * 2));
+ } else {
+ pupdr &= ~(0x3 << (pin_num * 2));
}
- sys_write32(otyper, p->OTYPER);
-
- if ((flags & GPIO_PULL_UP) != 0U) {
- pupdr &= ~(0x3 << (pin * 2));
- pupdr |= (0x1 << (pin * 2));
- } else if ((flags & GPIO_PULL_DOWN) != 0U) {
- pupdr &= ~(0x3 << (pin * 2));
- pupdr |= (0x2 << (pin * 2));
- } else {
- pupdr &= ~(0x3 << (pin * 2));
- }
- sys_write32(pupdr, p->PUPDR);
+ WRITE_REG(p->PUPDR, pupdr);
- return 0;
+ return 0;
}
int stm32f769_gpio_configure_af(struct device *dev, uint32_t pin, uint32_t flags)
{
-// const struct gpio_stm32f769_config *config = port->config;
- uint32_t port_idx = STM32F769_PORT_GET(pin);
+// const struct gpio_stm32f769_config *config = port->config;
GPIO_TypeDef *p = NULL;
if (dev == NULL) {
+ uint32_t port_idx = STM32F769_PORT_GET(pin);
p = stm32f769_get_port(port_idx);
} else {
p = dev->devptr;
}
-
- uint32_t moder = sys_read32(p->MODER);
- uint32_t ospeedr = sys_read32(p->OSPEEDR);
- uint32_t pupdr = sys_read32(p->PUPDR);
- uint32_t otyper = sys_read32(p->OTYPER);
- moder &= ~((0x3) << (pin * 2));
- moder |= ((0x2) << (pin * 2));
- sys_write32(moder, p->MODER);
+ uint32_t pin_num = pin & 0xf;
+ uint32_t moder = READ_REG(p->MODER);
+ uint32_t ospeedr = READ_REG(p->OSPEEDR);
+ uint32_t pupdr = READ_REG(p->PUPDR);
+ uint32_t otyper = READ_REG(p->OTYPER);
+
+ moder &= ~((0x3) << (pin_num * 2));
+ moder |= ((0x2) << (pin_num * 2));
+ WRITE_REG(p->MODER, moder);
// Low speed
- ospeedr &= ~((0x3) << (pin * 2));
- sys_write32(ospeedr, p->OSPEEDR);
+ ospeedr &= ~((0x3) << (pin_num * 2));
+ WRITE_REG(p->OSPEEDR, ospeedr);
if ((flags & GPIO_OPEN_DRAIN) != 0U) {
- otyper |= (1 << pin);
+ otyper |= (1 << pin_num);
} else {
- otyper &= ~(1 << pin);
+ otyper &= ~(1 << pin_num);
+ }
+ WRITE_REG(p->OTYPER, otyper);
+
+ if ((flags & GPIO_PULL_UP) != 0U) {
+ pupdr &= ~(0x3 << (pin_num * 2));
+ pupdr |= (0x1 << (pin_num * 2));
+ } else if ((flags & GPIO_PULL_DOWN) != 0U) {
+ pupdr &= ~(0x3 << (pin_num * 2));
+ pupdr |= (0x2 << (pin_num * 2));
+ } else {
+ pupdr &= ~(0x3 << (pin_num * 2));
}
- sys_write32(otyper, p->OTYPER);
-
- if ((flags & GPIO_PULL_UP) != 0U) {
- pupdr &= ~(0x3 << (pin * 2));
- pupdr |= (0x1 << (pin * 2));
- } else if ((flags & GPIO_PULL_DOWN) != 0U) {
- pupdr &= ~(0x3 << (pin * 2));
- pupdr |= (0x2 << (pin * 2));
- } else {
- pupdr &= ~(0x3 << (pin * 2));
- }
- sys_write32(pupdr, p->PUPDR);
+ WRITE_REG(p->PUPDR, pupdr);
- return 0;
+ return 0;
}
int stm32f769_gpio_configure(struct device *dev, uint32_t pin, uint32_t flags)
{
-// const struct gpio_stm32f769_config *config = port->config;
- uint32_t port_idx = STM32F769_PORT_GET(pin);
+// const struct gpio_stm32f769_config *config = port->config;
GPIO_TypeDef *p = NULL;
if (dev == NULL) {
+ uint32_t port_idx = STM32F769_PORT_GET(pin);
p = stm32f769_get_port(port_idx);
} else {
p = dev->devptr;
}
-
- uint32_t moder = sys_read32(p->MODER);
- uint32_t ospeedr = sys_read32(p->OSPEEDR);
- uint32_t pupdr = sys_read32(p->PUPDR);
- uint32_t otyper = sys_read32(p->OTYPER);
- if ((flags & GPIO_OUTPUT) != 0U) {
+ uint32_t pin_num = pin & 0xf;
+ uint32_t moder = READ_REG(p->MODER);
+ uint32_t ospeedr = READ_REG(p->OSPEEDR);
+ uint32_t pupdr = READ_REG(p->PUPDR);
+ uint32_t otyper = READ_REG(p->OTYPER);
+
+ if ((flags & GPIO_OUTPUT) != 0U) {
// GPIO mode
- moder &= ~((0x3) << (pin * 2));
- moder |= (0x01 << (pin * 2));
- sys_write32(moder, p->MODER);
+ moder &= ~((0x3) << (pin_num * 2));
+ moder |= (0x01 << (pin_num * 2));
+ WRITE_REG(p->MODER, moder);
// Low speed
- ospeedr &= ~((0x3) << (pin * 2));
- sys_write32(ospeedr, p->OSPEEDR);
-
- if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
- sys_write32(BIT(pin), p->BSRR);
- } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
- sys_write32(BIT(pin + 16), p->BSRR);
- }
- } else if ((flags & GPIO_INPUT) != 0U) {
+ ospeedr &= ~((0x3) << (pin_num * 2));
+ WRITE_REG(p->OSPEEDR, ospeedr);
+
+ if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
+ WRITE_REG(p->BSRR, BIT(pin_num));
+ } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
+ WRITE_REG(p->BSRR, BIT(pin_num + 16));
+ }
+ } else if ((flags & GPIO_INPUT) != 0U) {
// GPIO mode
- moder &= ~((0x3) << (pin * 2));
- sys_write32(moder, p->MODER);
+ moder &= ~((0x3) << (pin_num * 2));
+ WRITE_REG(p->MODER, moder);
// Low speed
- ospeedr &= ~((0x3) << (pin * 2));
- sys_write32(ospeedr, p->OSPEEDR);
- } else { // set mode ANALOG
+ ospeedr &= ~((0x3) << (pin_num * 2));
+ WRITE_REG(p->OSPEEDR, ospeedr);
+ } else { // set mode ANALOG
// GPIO mode
- moder |= ((0x3) << (pin * 2));
- sys_write32(moder, p->MODER);
+ moder |= ((0x3) << (pin_num * 2));
+ WRITE_REG(p->MODER, moder);
// Low speed
- ospeedr &= ~((0x3) << (pin * 2));
- sys_write32(ospeedr, p->OSPEEDR);
- }
+ ospeedr &= ~((0x3) << (pin_num * 2));
+ WRITE_REG(p->OSPEEDR, ospeedr);
+ }
if ((flags & GPIO_OPEN_DRAIN) != 0U) {
- otyper |= (1 << pin);
+ otyper |= (1 << pin_num);
} else {
- otyper &= ~(1 << pin);
+ otyper &= ~(1 << pin_num);
+ }
+ WRITE_REG(p->OTYPER, otyper);
+
+ if ((flags & GPIO_PULL_UP) != 0U) {
+ pupdr &= ~(0x3 << (pin_num * 2));
+ pupdr |= (0x1 << (pin_num * 2));
+ } else if ((flags & GPIO_PULL_DOWN) != 0U) {
+ pupdr &= ~(0x3 << (pin_num * 2));
+ pupdr |= (0x2 << (pin_num * 2));
+ } else {
+ pupdr &= ~(0x3 << (pin_num * 2));
}
- sys_write32(otyper, p->OTYPER);
-
- if ((flags & GPIO_PULL_UP) != 0U) {
- pupdr &= ~(0x3 << (pin * 2));
- pupdr |= (0x1 << (pin * 2));
- } else if ((flags & GPIO_PULL_DOWN) != 0U) {
- pupdr &= ~(0x3 << (pin * 2));
- pupdr |= (0x2 << (pin * 2));
- } else {
- pupdr &= ~(0x3 << (pin * 2));
- }
- sys_write32(pupdr, p->PUPDR);
+ WRITE_REG(p->PUPDR, pupdr);
- return 0;
+ return 0;
}
int stm32f769_gpio_init(struct device *dev)
{
uint32_t clkid = 0;
- switch (dev->devptr) {
- case GPIOA:
+ switch ((uint32_t)dev->devptr) {
+ case GPIOA_BASE:
clkid = STM32F769_CLOCK_GPIOA;
break;
- case GPIOB:
+ case GPIOB_BASE:
clkid = STM32F769_CLOCK_GPIOB;
break;
- case GPIOC:
+ case GPIOC_BASE:
clkid = STM32F769_CLOCK_GPIOC;
break;
- case GPIOD:
+ case GPIOD_BASE:
clkid = STM32F769_CLOCK_GPIOD;
break;
- case GPIOE:
+ case GPIOE_BASE:
clkid = STM32F769_CLOCK_GPIOE;
break;
- case GPIOF:
+ case GPIOF_BASE:
clkid = STM32F769_CLOCK_GPIOF;
break;
- case GPIOG:
+ case GPIOG_BASE:
clkid = STM32F769_CLOCK_GPIOG;
break;
- case GPIOH:
+ case GPIOH_BASE:
clkid = STM32F769_CLOCK_GPIOH;
break;
- case GPIOI:
+ case GPIOI_BASE:
clkid = STM32F769_CLOCK_GPIOI;
break;
- case GPIOJ:
+ case GPIOJ_BASE:
clkid = STM32F769_CLOCK_GPIOJ;
break;
- case GPIOK:
+ case GPIOK_BASE:
clkid = STM32F769_CLOCK_GPIOK;
break;
+ default:
+ return -1;
}
- stm32f769_clock_control_on(clkid);
+ stm32f769_clock_control_on(clkid);
- return 0;
+ return 0;
}
int stm32f769_gpio_read(struct device *dev, uint32_t pin) {
GPIO_TypeDef *p = dev->devptr;
- uint32_t state = sys_read32(p->IDR);
+ uint32_t state = READ_REG(p->IDR);
if (state & BIT(pin)) {
return 1;
}
@@ -224,8 +237,8 @@ int stm32f769_gpio_read(struct device *dev, uint32_t pin) {
void stm32f769_gpio_write(struct device *dev, uint32_t pin, int val) {
GPIO_TypeDef *p = dev->devptr;
if (val == 0) {
- sys_write32(BIT(pin + 16), p->BSRR);
+ WRITE_REG(p->BSRR, BIT(pin + 16));
} else {
- sys_write32(BIT(pin), p->BSRR);
+ WRITE_REG(p->BSRR, BIT(pin));
}
}
diff --git a/os/drivers/gpio/stm32f769_gpio.h b/os/drivers/gpio/stm32f769_gpio.h
index 832963ac..d009921c 100644
--- a/os/drivers/gpio/stm32f769_gpio.h
+++ b/os/drivers/gpio/stm32f769_gpio.h
@@ -3,8 +3,6 @@
#include <stdint.h>
-GPIO_TypeDef *stm32f769_get_port(unsigned int port_idx);
-uint16_t stm32f769_get_port_clkid(unsigned int port_idx);
int stm32f769_gpio_configure(struct device *dev, uint32_t pin, uint32_t flags);
int stm32f769_gpio_configure_analog(struct device *dev, uint32_t pin, uint32_t flags);
int stm32f769_gpio_configure_af(struct device *dev, uint32_t pin, uint32_t flags);
diff --git a/os/drivers/memory/stm32f7_mpu.c b/os/drivers/memory/stm32f7_mpu.c
index efc57b9f..fc45714b 100644
--- a/os/drivers/memory/stm32f7_mpu.c
+++ b/os/drivers/memory/stm32f7_mpu.c
@@ -38,7 +38,7 @@ int stm32f7_mpu_init(struct device *dev) {
MPU->RNR = MPU_REGION_NUMBER0;
/* Disable the Region */
- sys_clear_bit(MPU->RASR, MPU_RASR_ENABLE_Msk);
+ MODIFY_REG(MPU->RASR, MPU_RASR_ENABLE_Msk, 0);
/* Apply configuration */
MPU->RBAR = 0; // Base addr
diff --git a/os/drivers/pinctrl/stm32f769_pinctrl.c b/os/drivers/pinctrl/stm32f769_pinctrl.c
index ce45ec17..98b975f6 100644
--- a/os/drivers/pinctrl/stm32f769_pinctrl.c
+++ b/os/drivers/pinctrl/stm32f769_pinctrl.c
@@ -1,7 +1,12 @@
+#include <arch/sys_io.h>
+#include <arch/aarch32/armv7e_m/stm32f7/stm32f769xx.h>
#include <drivers/clock/stm32f769_clocks.h>
#include <drivers/clock/stm32f769_clock_control.h>
#include <drivers/gpio/stm32f769_gpio.h>
+#include <stddef.h>
+#include "stm32f769_pinctrl.h"
+
static const GPIO_TypeDef *stm32f769_port_addrs[] = {
GPIOA,
GPIOB,
@@ -30,65 +35,56 @@ static const uint16_t stm32f769_port_clkids[] = {
STM32F769_CLOCK_GPIOK,
};
-static GPIO_TypeDef *stm32f769_get_port(unsigned int port_idx) {
+GPIO_TypeDef *stm32f769_get_port(unsigned int port_idx) {
GPIO_TypeDef *p = stm32f769_port_addrs[port_idx];
return p;
}
-static uint16_t stm32f769_get_port_clkid(unsigned int port_idx) {
+uint16_t stm32f769_get_port_clkid(unsigned int port_idx) {
return stm32f769_port_clkids[port_idx];
}
void stm32f769_pinctrl_configure_pin(uint32_t pin)
{
- uint8_t port_idx;
- uint32_t port;
- uint32_t pin_num;
- uint32_t af;
- uint32_t dir;
- uint16_t clkid;
- //uint16_t strength;
-
- port_idx = STM32F769_PORT_GET(pin);
+ uint8_t port_idx;
+ uint32_t port;
+ uint32_t pin_num;
+ uint32_t af;
+ uint16_t clkid;
+ //uint16_t strength;
+
+ port_idx = STM32F769_PORT_GET(pin);
GPIO_TypeDef *p = stm32f769_get_port(port_idx);
clkid = stm32f769_get_port_clkid(port_idx);
- pin_num = STM32F769_PIN_GET(pin);
- af = STM32F769_AF_GET(pin);
- dir = STM32F769_DIR_GET(pin);
-
- clock_control_mik32_on(clkid);
-
- uint32_t pupd;
- uint32_t ds;
- uint32_t cfg;
- uint32_t dirin;
- uint32_t dirout;
+ pin_num = STM32F769_PIN_GET(pin);
+ af = STM32F769_AF_GET(pin);
- pupd = MIK32_PAD_PUPD(port);
- cfg = MIK32_PAD_CFG(port);
- ds = MIK32_PAD_DS(port);
- dirin = MIK32_GPIO_DIRIN(port);
- dirout = MIK32_GPIO_DIROUT(port);
+ stm32f769_clock_control_on(clkid);
- if (af != STM32F769_ANALOG) {
+ if (af != STM32F769_ANALOG) {
stm32f769_gpio_configure_af(NULL, pin, pin);
- } else {
- // set mode ANALOG
+ if (pin_num < 8) {
+ MODIFY_REG(p->AFR[0], (0xf << (pin_num * 4)), (af << (pin_num * 4)));
+ } else {
+ MODIFY_REG(p->AFR[1], (0xf << ((pin_num - 8) * 4)), (af << ((pin_num - 8) * 4)));
+ }
+ } else {
+ // set mode ANALOG
stm32f769_gpio_configure_analog(NULL, pin, pin);
- }
+ }
}
/* int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, */
-/* uintptr_t reg) */
+/* uintptr_t reg) */
/* { */
-/* ARG_UNUSED(reg); */
+/* ARG_UNUSED(reg); */
-/* for (uint8_t i = 0U; i < pin_cnt; i++) { */
-/* pinctrl_configure_pin(pins[i]); */
-/* } */
+/* for (uint8_t i = 0U; i < pin_cnt; i++) { */
+/* pinctrl_configure_pin(pins[i]); */
+/* } */
-/* return 0; */
+/* return 0; */
/* } */
diff --git a/os/drivers/pinctrl/stm32f769_pinctrl.h b/os/drivers/pinctrl/stm32f769_pinctrl.h
index 489faa68..85a6cb60 100644
--- a/os/drivers/pinctrl/stm32f769_pinctrl.h
+++ b/os/drivers/pinctrl/stm32f769_pinctrl.h
@@ -19,25 +19,37 @@
#define STM32F769_AF15 15U
#define STM32F769_ANALOG 16U
-#define STM32F769_PORT_MSK 0xFU
-#define STM32F769_PORT_POS 0U
#define STM32F769_PIN_MSK 0xFU
-#define STM32F769_PIN_POS 4U
-#define STM32F769_AF_MSK 0xFU
+#define STM32F769_PIN_POS 0U
+#define STM32F769_PORT_MSK 0xFU
+#define STM32F769_PORT_POS 4U
+#define STM32F769_AF_MSK 0x1FU
#define STM32F769_AF_POS 8U
-#define STM32F769_PORT_GET(pinmux) \
- (((pinmux) >> STM32F769_PORT_POS) & STM32F769_PORT_MSK)
+#define STM32F769_PORTA 0
+#define STM32F769_PORTB 1
+#define STM32F769_PORTC 2
+#define STM32F769_PORTD 3
+#define STM32F769_PORTE 4
+#define STM32F769_PORTF 5
+#define STM32F769_PORTG 6
+#define STM32F769_PORTH 7
+#define STM32F769_PORTI 8
+#define STM32F769_PORTJ 9
+#define STM32F769_PORTK 10
-#define STM32F769_PIN_GET(pinmux) \
- (((pinmux) >> STM32F769_PIN_POS) & STM32F769_PIN_MSK)
+#define STM32F769_PORT_GET(pinmux) \
+ (((pinmux) >> STM32F769_PORT_POS) & STM32F769_PORT_MSK)
-#define STM32F769_AF_GET(pinmux) \
- (((pinmux) >> STM32F769_AF_POS) & STM32F769_AF_MSK)
+#define STM32F769_PIN_GET(pinmux) \
+ (((pinmux) >> STM32F769_PIN_POS) & STM32F769_PIN_MSK)
+
+#define STM32F769_AF_GET(pinmux) \
+ (((pinmux) >> STM32F769_AF_POS) & STM32F769_AF_MSK)
/**
- * - 0..3: port
- * - 4..7: pin
+ * - 0..3: pin
+ * - 4..7: port
* - 8..13: af
*
* port: Port ('A'..'K')
@@ -45,9 +57,13 @@
* af: Alternate function (ANALOG, AFx, x=0..15)
*/
-#define STM32F769_PINMUX_AF(port, pin, af) \
- ((((port) & STM32F769_PORT_MSK) << STM32F769_PORT_POS) | \
- (((pin) & STM32F769_PIN_MSK) << STM32F769_PIN_POS) | \
- (((STM32F769_ ## af) & STM32F769_AF_MSK) << STM32F769_AF_POS))
+#define STM32F769_PINMUX_AF(port, pin, af) \
+ ((((port) & STM32F769_PORT_MSK) << STM32F769_PORT_POS) | \
+ (((pin) & STM32F769_PIN_MSK) << STM32F769_PIN_POS) | \
+ (((STM32F769_ ## af) & STM32F769_AF_MSK) << STM32F769_AF_POS))
+
+void stm32f769_pinctrl_configure_pin(uint32_t pin);
+GPIO_TypeDef *stm32f769_get_port(unsigned int port_idx);
+uint16_t stm32f769_get_port_clkid(unsigned int port_idx);
#endif/*__DT_BINDINGS_PINCTRL_STM32F769_AF_H_ */
diff --git a/os/drivers/uart/stm32f7_uart.c b/os/drivers/uart/stm32f7_uart.c
index 2acb038e..76f67ae9 100644
--- a/os/drivers/uart/stm32f7_uart.c
+++ b/os/drivers/uart/stm32f7_uart.c
@@ -25,6 +25,7 @@ inline static void __uart_enable(struct device *dev) {
int stm32f7_uart_init(struct device *dev) {
USART_TypeDef *p = dev->devptr;
stm32f7_uart_deinit(dev);
+
uint32_t clk_rate = 0;
uint32_t parity = 0;
uint32_t stop_bits = 0;
@@ -57,6 +58,8 @@ int stm32f7_uart_init(struct device *dev) {
case UART8_BASE:
stm32f769_clock_control_get_rate(STM32F769_CLOCK_UART8, &clk_rate);
break;
+ default:
+ return -1;
}
switch (uart->data_bits) {
@@ -109,16 +112,16 @@ int stm32f7_uart_init(struct device *dev) {
}
uint32_t cr1 = word_length | parity | USART_CR1_TE | USART_CR1_RE;
- sys_write32(cr1, p->CR1);
- cr1 = sys_read32(p->CR1);
+ WRITE_REG(p->CR1, cr1);
+ cr1 = READ_REG(p->CR1);
uint32_t cr2 = stop_bits;
- sys_write32(cr2, p->CR2);
- cr2 = sys_read32(p->CR2);
+ WRITE_REG(p->CR2, cr2);
+ cr2 = READ_REG(p->CR2);
uint32_t cr3 = 0;
- sys_write32(cr3, p->CR3);
- cr3 = sys_read32(p->CR3);
+ WRITE_REG(p->CR3, cr3);
+ cr3 = READ_REG(p->CR3);
uint32_t div = (clk_rate + ((uart->baudrate)/2U)) / (uart->baudrate);
if ((div >= UART_BRR_MIN) && (div <= UART_BRR_MAX)) {
@@ -127,10 +130,10 @@ int stm32f7_uart_init(struct device *dev) {
return -1;
}
- sys_clear_bits(p->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- sys_clear_bits(p->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ CLEAR_BIT(p->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(p->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- stm32f7_uart_init(dev);
+ __uart_enable(dev);
return 0;
}
generated by cgit v1.2.3 (git 2.46.0) at 2026-01-09 16:47:46 +0000