diff options
Diffstat (limited to 'os/drivers')
| -rw-r--r-- | os/drivers/clock/stm32f769_clock_control.c | 499 | ||||
| -rw-r--r-- | os/drivers/clock/stm32f769_clock_control.h | 2 | ||||
| -rw-r--r-- | os/drivers/clock/stm32f769_clocks.h | 27 | ||||
| -rw-r--r-- | os/drivers/clock/stm32f769_rcc.h | 12 | ||||
| -rw-r--r-- | os/drivers/clock/stm32f769_rcc_ex.h | 418 | ||||
| -rw-r--r-- | os/drivers/gpio/gpio.h | 72 | ||||
| -rw-r--r-- | os/drivers/gpio/stm32f769_gpio.c | 244 | ||||
| -rw-r--r-- | os/drivers/gpio/stm32f769_gpio.h | 13 | ||||
| -rw-r--r-- | os/drivers/memory/stm32f7_mpu.c | 8 | ||||
| -rw-r--r-- | os/drivers/pinctrl/pinctrl.h | 6 | ||||
| -rw-r--r-- | os/drivers/pinctrl/stm32f769_pinctrl.c | 90 | ||||
| -rw-r--r-- | os/drivers/pinctrl/stm32f769_pinctrl.h | 69 | ||||
| -rw-r--r-- | os/drivers/uart/stm32f7_uart.c | 168 | ||||
| -rw-r--r-- | os/drivers/uart/stm32f7_uart.h | 12 | ||||
| -rw-r--r-- | os/drivers/uart/uart.h | 37 |
15 files changed, 1428 insertions, 249 deletions
diff --git a/os/drivers/clock/stm32f769_clock_control.c b/os/drivers/clock/stm32f769_clock_control.c index d62b5799..e9b6bf2a 100644 --- a/os/drivers/clock/stm32f769_clock_control.c +++ b/os/drivers/clock/stm32f769_clock_control.c @@ -1,12 +1,35 @@ #include <arch/sys_io.h> -#include "stm32f769_clock_control.h" +#include <arch/aarch32/armv7e_m/stm32f7/stm32f769xx.h> #include <stdint.h> +#include "stm32f769_clock_control.h" +#include "stm32f769_rcc.h" + #include "errno.h" #include "stm32f769_clocks.h" +#define TICK_INT_PRIORITY 0x0FU + #define STM32F769_CLOCK_ID_OFFSET(id) (((id) >> 6U) & 0xFFU) -#define STM32F769_CLOCK_ID_BIT(id) ((id)&0x1FU) +#define STM32F769_CLOCK_ID_BIT(id) (id & 0x1FU) + +#define HSI_VALUE 16000000 + +enum CLK_SOURCE { + CS_UNKNOWN = 0, + CS_HSI, + CS_HSE, + CS_PLL_HSI, + CS_PLL_HSE, +}; + +struct rcc_clk_init { + uint32_t ClockType; + uint32_t SYSCLKSource; + uint32_t AHBCLKDivider; + uint32_t APB1CLKDivider; + uint32_t APB2CLKDivider; +}; volatile uint64_t uptime_ctr; @@ -15,10 +38,12 @@ void SysTick_Handler(void) { } int stm32f769_clock_control_on(uint16_t id) { + uint32_t addr = RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id); + uint32_t bit = STM32F769_CLOCK_ID_BIT(id); sys_set_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id), STM32F769_CLOCK_ID_BIT(id)); - int ret = sys_test_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id), - STM32F769_CLOCK_ID_BIT(id)); + volatile int ret = sys_test_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id), + STM32F769_CLOCK_ID_BIT(id)); (void)ret; return 0; } @@ -57,7 +82,7 @@ static uint32_t __get_ahb_div(uint32_t val) { } } -static uint32_t __get_apb_div(uint32_t val) { +static uint32_t __get_apb1_div(uint32_t val) { switch (val) { case RCC_CFGR_PPRE1_DIV2: return 2; @@ -73,17 +98,160 @@ static uint32_t __get_apb_div(uint32_t val) { } } +static uint32_t __get_apb2_div(uint32_t val) { + switch (val) { + case RCC_CFGR_PPRE2_DIV2: + return 2; + case RCC_CFGR_PPRE2_DIV4: + return 4; + case RCC_CFGR_PPRE2_DIV8: + return 8; + case RCC_CFGR_PPRE2_DIV16: + return 16; + case RCC_CFGR_PPRE2_DIV1: + default: + return 1; + } +} + +uint32_t __get_sysclk(void) +{ + uint64_t plln = 0; + uint32_t pllm = 0, pllvco = 0, pllp = 0; + uint32_t clk = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + clk = HSI_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + clk = CONFIG_BOARD_HSE_CLK; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + plln = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) CONFIG_BOARD_HSE_CLK * ((uint64_t)plln))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + + clk = pllvco / pllp; + break; + } + default: + { + clk = HSI_VALUE; + break; + } + } + return clk; +} + +#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN) +#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN)) +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) +#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 +#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN) +#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN)) +#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY + +static int __enable_overdrive(void) +{ + uint32_t tickstart = 0; + + stm32f769_clock_control_on(STM32F769_CLOCK_PWR); + + __HAL_PWR_OVERDRIVE_ENABLE(); + tickstart = uptime_ctr; + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((uptime_ctr - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return -1; + } + } + + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + tickstart = uptime_ctr; + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((uptime_ctr - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return -1; + } + } + return 0; +} + +/* HAL_StatusTypeDef __disable_overdrive(void) */ +/* { */ +/* uint32_t tickstart = 0; */ + +/* __HAL_RCC_PWR_CLK_ENABLE(); */ + +/* /\* Disable the Over-drive switch *\/ */ +/* __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); */ + +/* /\* Get tick *\/ */ +/* tickstart = HAL_GetTick(); */ + +/* while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) */ +/* { */ +/* if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) */ +/* { */ +/* return HAL_TIMEOUT; */ +/* } */ +/* } */ + +/* /\* Disable the Over-drive *\/ */ +/* __HAL_PWR_OVERDRIVE_DISABLE(); */ + +/* /\* Get tick *\/ */ +/* tickstart = HAL_GetTick(); */ + +/* while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) */ +/* { */ +/* if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) */ +/* { */ +/* return HAL_TIMEOUT; */ +/* } */ +/* } */ + +/* return HAL_OK; */ +/* } */ + int stm32f769_clock_control_get_rate(uint16_t id, uint32_t *rate) { uint32_t clk_offt = STM32F769_CLOCK_ID_OFFSET(id); uint32_t ahb_div = __get_ahb_div(RCC->CFGR & RCC_CFGR_HPRE_Msk); - uint32_t apb1_div = __get_apb_div(RCC->CFGR & RCC_CFGR_PPRE1_Msk); - uint32_t apb2_div = __get_apb_div(RCC->CFGR & RCC_CFGR_PPRE2_Msk); - uint32_t ahb_rate = CONFIG_BOARD_SYS_CLK / ahb_div; + uint32_t apb1_div = __get_apb1_div(RCC->CFGR & RCC_CFGR_PPRE1_Msk); + uint32_t apb2_div = __get_apb2_div(RCC->CFGR & RCC_CFGR_PPRE2_Msk); + uint32_t ahb_rate = __get_sysclk() / ahb_div; switch (clk_offt) { case STM32F769_RCC_SYS_SET_OFFSET: - *rate = CONFIG_BOARD_SYS_CLK; + *rate = __get_sysclk(); break; case STM32F769_RCC_AHB1_SET_OFFSET: *rate = ahb_rate; @@ -110,43 +278,197 @@ int stm32f769_clock_control_get_rate(uint16_t id, uint32_t *rate) #define RCC_FLAG_MASK ((uint8_t)0x1F) #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ - (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ - ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ - ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ - ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) - -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) +/* #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ */ +/* (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ */ +/* ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ */ +/* ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ */ +/* ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ */ +/* ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) */ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#define PLL_TIMEOUT_VALUE 2 +//#define PLL_TIMEOUT_VALUE 2 +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + +static int __deinit_clk(void) +{ + uint32_t tickstart; + + tickstart = uptime_ctr; + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0) + { + if ((uptime_ctr - tickstart) > HSI_TIMEOUT_VALUE) + { + return -ETIMEDOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = uptime_ctr; + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0) + { + if ((uptime_ctr - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return -ETIMEDOUT; + } + } + + /* Get Start Tick */ + tickstart = uptime_ctr; + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0) + { + if ((uptime_ctr - tickstart) > HSE_TIMEOUT_VALUE) + { + return -ETIMEDOUT; + } + } + + /* Get Start Tick */ + tickstart = uptime_ctr; + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0) + { + if ((uptime_ctr - tickstart) > PLL_TIMEOUT_VALUE) + { + return -ETIMEDOUT; + } + } + + /* Get Start Tick */ + tickstart = uptime_ctr; + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != 0) + { + if ((uptime_ctr - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return -ETIMEDOUT; + } + } + + /* Get Start Tick */ + tickstart = uptime_ctr; + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != 0) + { + if ((uptime_ctr - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return -ETIMEDOUT; + } + } + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U; + + /* Reset PLLI2SCFGR register to default value */ + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; + + /* Reset PLLSAICFGR register to default value */ + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U; + + /* Disable all interrupts */ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + return stm32f769_init_tick(); +} int stm32f769_clock_control_init(struct device *dev) { uint32_t tickstart; - uint32_t pll_config; - FlagStatus pwrclkchanged = RESET; + enum CLK_SOURCE cs = CS_UNKNOWN; + int ret = 0; + + uint32_t clk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + uint32_t pllcfgr = READ_REG(RCC->PLLCFGR); + uint32_t rcccr = READ_REG(RCC->CR); + + switch (clk_source) { + case RCC_SYSCLKSOURCE_STATUS_HSE: + cs = CS_HSE; + break; + case RCC_SYSCLKSOURCE_STATUS_HSI: + cs = CS_HSI; + break; + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE) { + cs = CS_PLL_HSE; + } else if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI) { + cs = CS_PLL_HSI; + } else { + while (1) {}; + } + break; + default: + while (1) {}; + break; + } + + ret = __deinit_clk(); + if (ret != 0) { + while (1) {}; + } if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) { - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0)) {// && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return -1; } } else { #if defined(CONFIG_BOARD_HSE_CLK) #if CONFIG_BOARD_HSE_BYP == 1 - SET_BIT(RCC->CR, RCC_CR_HSEBYP); - SET_BIT(RCC->CR, RCC_CR_HSEON); + RCC->CR |= RCC_CR_HSEBYP; + RCC->CR |= RCC_CR_HSEON; #else - SET_BIT(RCC->CR, RCC_CR_HSEON); + RCC->CR |= RCC_CR_HSEON; #endif /* Get Start Tick*/ tickstart = uptime_ctr; /* Wait till HSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0) { if ((uptime_ctr - tickstart) > HSE_STARTUP_TIMEOUT) { return -1; } @@ -164,8 +486,8 @@ int stm32f769_clock_control_init(struct device *dev) tickstart = uptime_ctr; /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0) { + if ((uptime_ctr - tickstart) > PLL_TIMEOUT_VALUE) { return -1; } } @@ -180,15 +502,132 @@ int stm32f769_clock_control_init(struct device *dev) tickstart = uptime_ctr; /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0) { + if ((uptime_ctr - tickstart) > PLL_TIMEOUT_VALUE) { return -1; } } } + + if (__enable_overdrive() != 0) { + while (1) {}; + } + + if (FLASH_ACR_LATENCY_7WS > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_ACR_LATENCY_7WS); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_ACR_LATENCY_7WS) + { + while (1) {}; + return -1; + } + } + + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0) + { + while (1) {}; + return -1; + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_PLLCLK); + + /* Get Start Tick*/ + tickstart = uptime_ctr; + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_SYSCLKSOURCE_PLLCLK << RCC_CFGR_SWS_Pos)) + { + if ((uptime_ctr - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + while (1) {}; + return -1; + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_ACR_LATENCY_7WS < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_ACR_LATENCY_7WS); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_ACR_LATENCY_7WS) + { + return -1; + } + } + + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV4); + + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_HCLK_DIV2) << 3)); + + SystemCoreClock = __get_sysclk() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + stm32f769_init_tick(); return 0; } + +static void __rcc_get_clock_config(struct rcc_clk_init *clkinit, uint32_t *flash_latency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + clkinit->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + clkinit->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + clkinit->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + clkinit->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + clkinit->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *flash_latency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +int stm32f769_init_tick(void) +{ + uint32_t TickPriority = TICK_INT_PRIORITY; + struct rcc_clk_init clkconfig; + uint32_t flash_latency; + + uint32_t prioritygroup = 0x00; + prioritygroup = NVIC_GetPriorityGrouping(); + NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, TickPriority, 0)); + //__nvic_setpriority(SysTick_IRQn, TickPriority, 0U); + + /* Enable the TIM6 global Interrupt */ + NVIC_EnableIRQ(SysTick_IRQn); + + /* Get clock configuration */ + __rcc_get_clock_config(&clkconfig, &flash_latency); + + uint32_t ahb1_rate = 0; + stm32f769_clock_control_get_rate(STM32F769_CLOCK_GPIOA, &ahb1_rate); + uint32_t sys_rate = 0; + stm32f769_clock_control_get_rate(STM32F769_CLOCK_SYS, &sys_rate); + + MODIFY_REG(SysTick->LOAD, SysTick_LOAD_RELOAD_Msk, ((ahb1_rate) / 1000) - 1); + CLEAR_BIT(SysTick->VAL, SysTick_VAL_CURRENT_Msk); + SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk); + + /* Return function status */ + return 0; +} + + /* static enum clock_control_status */ /* clock_control_mik32_get_status(uint16_t id) */ /* { */ diff --git a/os/drivers/clock/stm32f769_clock_control.h b/os/drivers/clock/stm32f769_clock_control.h index 9d553f61..23cfb906 100644 --- a/os/drivers/clock/stm32f769_clock_control.h +++ b/os/drivers/clock/stm32f769_clock_control.h @@ -2,10 +2,12 @@ #define __STM32F769_CLOCK_CONTROL_H__ #include <stdint.h> +#include <drivers/include/device.h> int stm32f769_clock_control_on(uint16_t id); int stm32f769_clock_control_off(uint16_t id); int stm32f769_clock_control_get_rate(uint16_t id, uint32_t *rate); int stm32f769_clock_control_init(struct device *dev); +int stm32f769_init_tick (void); #endif/*__STM32F769_CLOCK_CONTROL_H__*/ diff --git a/os/drivers/clock/stm32f769_clocks.h b/os/drivers/clock/stm32f769_clocks.h index 5ff690bc..b65c2bd5 100644 --- a/os/drivers/clock/stm32f769_clocks.h +++ b/os/drivers/clock/stm32f769_clocks.h @@ -12,6 +12,31 @@ #define STM32F769_RCC_APB1_SET_OFFSET 0x40U #define STM32F769_RCC_APB2_SET_OFFSET 0x44U -#ddefine STM32F769_CLOCK_TIM6 STM32F769_CLOCK_CONFIG(APB1_SET, 4U) +#define STM32F769_CLOCK_SYS STM32F769_CLOCK_CONFIG(SYS_SET, 0) + +#define STM32F769_CLOCK_TIM6 STM32F769_CLOCK_CONFIG(APB1_SET, 4U) + +#define STM32F769_CLOCK_USART1 STM32F769_CLOCK_CONFIG(APB2_SET, 4U) +#define STM32F769_CLOCK_USART2 STM32F769_CLOCK_CONFIG(APB1_SET, 17U) +#define STM32F769_CLOCK_USART3 STM32F769_CLOCK_CONFIG(APB1_SET, 18U) +#define STM32F769_CLOCK_UART4 STM32F769_CLOCK_CONFIG(APB1_SET, 19U) +#define STM32F769_CLOCK_UART5 STM32F769_CLOCK_CONFIG(APB1_SET, 20U) +#define STM32F769_CLOCK_USART6 STM32F769_CLOCK_CONFIG(APB2_SET, 5U) +#define STM32F769_CLOCK_UART7 STM32F769_CLOCK_CONFIG(APB1_SET, 30U) +#define STM32F769_CLOCK_UART8 STM32F769_CLOCK_CONFIG(APB1_SET, 31U) + +#define STM32F769_CLOCK_GPIOA STM32F769_CLOCK_CONFIG(AHB1_SET, 0U) +#define STM32F769_CLOCK_GPIOB STM32F769_CLOCK_CONFIG(AHB1_SET, 1U) +#define STM32F769_CLOCK_GPIOC STM32F769_CLOCK_CONFIG(AHB1_SET, 2U) +#define STM32F769_CLOCK_GPIOD STM32F769_CLOCK_CONFIG(AHB1_SET, 3U) +#define STM32F769_CLOCK_GPIOE STM32F769_CLOCK_CONFIG(AHB1_SET, 4U) +#define STM32F769_CLOCK_GPIOF STM32F769_CLOCK_CONFIG(AHB1_SET, 5U) +#define STM32F769_CLOCK_GPIOG STM32F769_CLOCK_CONFIG(AHB1_SET, 6U) +#define STM32F769_CLOCK_GPIOH STM32F769_CLOCK_CONFIG(AHB1_SET, 7U) +#define STM32F769_CLOCK_GPIOI STM32F769_CLOCK_CONFIG(AHB1_SET, 8U) +#define STM32F769_CLOCK_GPIOJ STM32F769_CLOCK_CONFIG(AHB1_SET, 9U) +#define STM32F769_CLOCK_GPIOK STM32F769_CLOCK_CONFIG(AHB1_SET, 10U) + +#define STM32F769_CLOCK_PWR STM32F769_CLOCK_CONFIG(APB1_SET, 28U) #endif /* __DD_STM32F769_CLOCKS_H__ */ diff --git a/os/drivers/clock/stm32f769_rcc.h b/os/drivers/clock/stm32f769_rcc.h index 50c1627f..21e4f419 100644 --- a/os/drivers/clock/stm32f769_rcc.h +++ b/os/drivers/clock/stm32f769_rcc.h @@ -24,11 +24,11 @@ #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" +//#include "stm32f7xx_hal_def.h" /* Include RCC HAL Extended module */ /* (include on top of file since RCC structures are defined in extended file) */ -#include "stm32f7xx_hal_rcc_ex.h" +#include "stm32f769_rcc_ex.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ @@ -1121,7 +1121,7 @@ typedef struct */ /* Include RCC HAL Extension module */ -#include "stm32f7xx_hal_rcc_ex.h" +#include "stm32f769_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_Exported_Functions @@ -1132,9 +1132,9 @@ typedef struct * @{ */ /* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/* HAL_StatusTypeDef HAL_RCC_DeInit(void); */ +/* HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); */ +/* HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); */ /** * @} */ diff --git a/os/drivers/clock/stm32f769_rcc_ex.h b/os/drivers/clock/stm32f769_rcc_ex.h index 7f749fd4..075060bb 100644 --- a/os/drivers/clock/stm32f769_rcc_ex.h +++ b/os/drivers/clock/stm32f769_rcc_ex.h @@ -24,7 +24,7 @@ #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" +//#include "stm32f7xx_hal_def.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ @@ -61,7 +61,7 @@ typedef struct uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -86,7 +86,7 @@ typedef struct This parameter will be used only when PLLI2S is selected as Clock Source SAI */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ @@ -107,7 +107,7 @@ typedef struct This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ @@ -207,12 +207,12 @@ typedef struct This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ @@ -233,7 +233,7 @@ typedef struct * @{ */ #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) @@ -259,10 +259,10 @@ typedef struct #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -272,7 +272,7 @@ typedef struct */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider * @{ */ @@ -323,7 +323,7 @@ typedef struct #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @@ -336,7 +336,7 @@ typedef struct #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @@ -521,7 +521,7 @@ typedef struct */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source * @{ */ @@ -532,7 +532,7 @@ typedef struct */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source * @{ */ @@ -550,9 +550,9 @@ typedef struct /** * @} */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source * @{ */ @@ -561,7 +561,7 @@ typedef struct /** * @} */ -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ /** * @} @@ -697,7 +697,7 @@ typedef struct } while(0) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -722,7 +722,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) @@ -739,15 +739,15 @@ typedef struct #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) /** * @brief Enable ETHERNET clock. @@ -801,7 +801,7 @@ typedef struct __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -809,7 +809,7 @@ typedef struct * using it. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -819,9 +819,9 @@ typedef struct UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ @@ -830,7 +830,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -995,7 +995,7 @@ typedef struct } while(0) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) ||\ defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1005,9 +1005,9 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ @@ -1015,7 +1015,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1122,7 +1122,7 @@ typedef struct } while(0) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1155,7 +1155,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) @@ -1168,14 +1168,14 @@ typedef struct #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) ||\ defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) @@ -1190,13 +1190,13 @@ typedef struct #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || || STM32F750xx */ /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1236,7 +1236,7 @@ typedef struct } while(0) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ @@ -1244,7 +1244,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || || STM32F730xx */ #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1327,7 +1327,7 @@ typedef struct } while(0) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1336,7 +1336,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1354,7 +1354,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ @@ -1362,9 +1362,9 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ @@ -1372,9 +1372,9 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ @@ -1390,7 +1390,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1406,9 +1406,9 @@ typedef struct #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) @@ -1421,23 +1421,23 @@ typedef struct #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ @@ -1474,12 +1474,12 @@ typedef struct #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) @@ -1496,15 +1496,15 @@ typedef struct #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) /** * @brief Enable ETHERNET clock. @@ -1527,7 +1527,7 @@ typedef struct #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1553,16 +1553,16 @@ typedef struct #endif /* STM32F732xx || STM32F733xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1590,9 +1590,9 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) @@ -1617,9 +1617,9 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) @@ -1634,7 +1634,7 @@ typedef struct #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) @@ -1645,15 +1645,15 @@ typedef struct #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) ||\ defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ /** @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1676,27 +1676,27 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ @@ -1717,27 +1717,27 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ @@ -1778,7 +1778,7 @@ typedef struct #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) @@ -1789,7 +1789,7 @@ typedef struct #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release AHB2 peripheral reset. */ @@ -1801,10 +1801,10 @@ typedef struct #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) @@ -1819,11 +1819,11 @@ typedef struct #endif /* STM32F732xx || STM32F733xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release AHB3 peripheral reset */ @@ -1847,9 +1847,9 @@ typedef struct #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) @@ -1874,9 +1874,9 @@ typedef struct #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) @@ -1892,7 +1892,7 @@ typedef struct #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) @@ -1903,7 +1903,7 @@ typedef struct #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release APB2 peripheral reset. */ @@ -1921,16 +1921,16 @@ typedef struct #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ @@ -1949,37 +1949,37 @@ typedef struct #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ /** * @} */ @@ -2034,7 +2034,7 @@ typedef struct #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) @@ -2051,7 +2051,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2060,16 +2060,16 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) @@ -2118,9 +2118,9 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) @@ -2145,9 +2145,9 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) @@ -2163,15 +2163,15 @@ typedef struct #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) ||\ defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) @@ -2182,7 +2182,7 @@ typedef struct #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2206,9 +2206,9 @@ typedef struct #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) @@ -2226,31 +2226,31 @@ typedef struct #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ @@ -2309,7 +2309,7 @@ typedef struct #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) @@ -2326,7 +2326,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2335,16 +2335,16 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F767xx) || defined(CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) @@ -2394,14 +2394,14 @@ typedef struct #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) ||\ defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) @@ -2427,14 +2427,14 @@ typedef struct #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) ||\ defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) @@ -2450,7 +2450,7 @@ typedef struct #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) @@ -2461,7 +2461,7 @@ typedef struct #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2485,20 +2485,20 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) @@ -2516,33 +2516,33 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ /*------------------------------- PLL Configuration --------------------------*/ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * @param __RCC_PLLSource__ specifies the PLL entry clock source. @@ -2611,7 +2611,7 @@ typedef struct ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ /*---------------------------------------------------------------------------------------------*/ /** @brief Macro to configure the Timers clocks prescalers @@ -2737,7 +2737,7 @@ typedef struct #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) ||\ defined (STM32F750xx) /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. * @note This function must be called before enabling the PLLSAI. @@ -2747,7 +2747,7 @@ typedef struct */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Macro to configure SAI1 clock source selection. * @note This function must be called before enabling PLLSAI, PLLI2S and @@ -3161,7 +3161,7 @@ typedef struct #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. * This parameter can be one of the following values: @@ -3177,9 +3177,9 @@ typedef struct * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock */ #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the DFSDM1 clock * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. * This parameter can be one of the following values: @@ -3211,9 +3211,9 @@ typedef struct * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock */ #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#if defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F779xx) /** @brief Macro to configure the DSI clock. * @param __DSI_CLKSOURCE__ specifies the DSI clock source. * This parameter can be one of the following values: @@ -3228,7 +3228,7 @@ typedef struct * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. */ #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) -#endif /* STM32F769xx || STM32F779xx */ +#endif /* CONFIG_ARCH_CPU_STM32F769 || STM32F779xx */ /** * @} */ @@ -3237,13 +3237,13 @@ typedef struct /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); -HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +/* HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); */ +/* void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); */ +/* uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); */ +/* HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); */ +/* HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); */ +/* HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); */ +/* HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); */ /** * @} */ @@ -3303,7 +3303,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#elif defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ @@ -3383,12 +3383,12 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); #endif /* STM32F746xx || STM32F756xx || STM32F750xx */ #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ ((VALUE) == RCC_PLLI2SP_DIV4) ||\ ((VALUE) == RCC_PLLI2SP_DIV6) ||\ ((VALUE) == RCC_PLLI2SP_DIV8)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F750xx */ #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -3501,7 +3501,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ @@ -3519,18 +3519,18 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F767xx) || defined (CONFIG_ARCH_CPU_STM32F769) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || CONFIG_ARCH_CPU_STM32F769 || STM32F777xx || STM32F779xx */ /** * @} diff --git a/os/drivers/gpio/gpio.h b/os/drivers/gpio/gpio.h new file mode 100644 index 00000000..df041a6c --- /dev/null +++ b/os/drivers/gpio/gpio.h @@ -0,0 +1,72 @@ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#include <stdint.h> + +#define GPIO_INPUT (1U << 16) +#define GPIO_OUTPUT (1U << 17) +#define GPIO_DISCONNECTED 0 + +#define GPIO_OUTPUT_INIT_LOW (1U << 18) +#define GPIO_OUTPUT_INIT_HIGH (1U << 19) +#define GPIO_OUTPUT_INIT_LOGICAL (1U << 20) + +#define GPIO_OUTPUT_LOW (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW) +#define GPIO_OUTPUT_HIGH (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH) +#define GPIO_OUTPUT_INACTIVE (GPIO_OUTPUT | \ + GPIO_OUTPUT_INIT_LOW | \ + GPIO_OUTPUT_INIT_LOGICAL) +#define GPIO_OUTPUT_ACTIVE (GPIO_OUTPUT | \ + GPIO_OUTPUT_INIT_HIGH | \ + GPIO_OUTPUT_INIT_LOGICAL) + +#define GPIO_INT_DISABLE (1U << 21) +#define GPIO_INT_ENABLE (1U << 22) +#define GPIO_INT_LEVELS_LOGICAL (1U << 23) +#define GPIO_INT_EDGE (1U << 24) +#define GPIO_INT_LOW_0 (1U << 25) +#define GPIO_INT_HIGH_1 (1U << 26) + +#define GPIO_INT_MASK (GPIO_INT_DISABLE | \ + GPIO_INT_ENABLE | \ + GPIO_INT_LEVELS_LOGICAL | \ + GPIO_INT_EDGE | \ + GPIO_INT_LOW_0 | \ + GPIO_INT_HIGH_1) +#define GPIO_INT_EDGE_RISING (GPIO_INT_ENABLE | \ + GPIO_INT_EDGE | \ + GPIO_INT_HIGH_1) +#define GPIO_INT_EDGE_FALLING (GPIO_INT_ENABLE | \ + GPIO_INT_EDGE | \ + GPIO_INT_LOW_0) +#define GPIO_INT_EDGE_BOTH (GPIO_INT_ENABLE | \ + GPIO_INT_EDGE | \ + GPIO_INT_LOW_0 | \ + GPIO_INT_HIGH_1) +#define GPIO_INT_LEVEL_LOW (GPIO_INT_ENABLE | \ + GPIO_INT_LOW_0) +#define GPIO_INT_LEVEL_HIGH (GPIO_INT_ENABLE | \ + GPIO_INT_HIGH_1) +#define GPIO_INT_EDGE_TO_INACTIVE (GPIO_INT_ENABLE | \ + GPIO_INT_LEVELS_LOGICAL | \ + GPIO_INT_EDGE | \ + GPIO_INT_LOW_0) +#define GPIO_INT_EDGE_TO_ACTIVE (GPIO_INT_ENABLE | \ + GPIO_INT_LEVELS_LOGICAL | \ + GPIO_INT_EDGE | \ + GPIO_INT_HIGH_1) +#define GPIO_INT_LEVEL_INACTIVE (GPIO_INT_ENABLE | \ + GPIO_INT_LEVELS_LOGICAL | \ + GPIO_INT_LOW_0) +#define GPIO_INT_LEVEL_ACTIVE (GPIO_INT_ENABLE | \ + GPIO_INT_LEVELS_LOGICAL | \ + GPIO_INT_HIGH_1) +#define GPIO_DIR_MASK (GPIO_INPUT | GPIO_OUTPUT) + +#define GPIO_OPEN_DRAIN (1 << 27) +#define GPIO_OPEN_SOURCE (1 << 28) +#define GPIO_PULL_UP (1 << 29) +#define GPIO_PULL_DOWN (1 << 30) +#define GPIO_INT_WAKEUP (1 << 31) + +#endif/*__GPIO_H__*/ diff --git a/os/drivers/gpio/stm32f769_gpio.c b/os/drivers/gpio/stm32f769_gpio.c new file mode 100644 index 00000000..ce2561ae --- /dev/null +++ b/os/drivers/gpio/stm32f769_gpio.c @@ -0,0 +1,244 @@ +#include <arch/sys_io.h> +#include <arch/aarch32/armv7e_m/stm32f7/stm32f769xx.h> +#include <drivers/pinctrl/stm32f769_pinctrl.h> +#include <drivers/clock/stm32f769_clocks.h> +#include <drivers/clock/stm32f769_clock_control.h> + +#include <stddef.h> + +#include "gpio.h" +/* #include "memory_map.h" */ +/* #include "soc_gpio.h" */ +/* #include "soc.h" */ +/* #include "clocks.h" */ +/* #include "clock_control.h" */ + +int stm32f769_gpio_configure_analog(struct device *dev, uint32_t pin, uint32_t flags) +{ +// const struct gpio_stm32f769_config *config = port->config; + GPIO_TypeDef *p = NULL; + if (dev == NULL) { + uint32_t port_idx = STM32F769_PORT_GET(pin); + p = stm32f769_get_port(port_idx); + } else { + p = dev->devptr; + } + + uint32_t moder = READ_REG(p->MODER); + uint32_t ospeedr = READ_REG(p->OSPEEDR); + uint32_t pupdr = READ_REG(p->PUPDR); + uint32_t otyper = READ_REG(p->OTYPER); + + uint32_t pin_num = pin & 0xf; + + moder |= ((0x3) << (pin_num * 2)); + WRITE_REG(p->MODER, moder); + + // Low speed + ospeedr &= ~((0x3) << (pin_num * 2)); + WRITE_REG(p->OSPEEDR, ospeedr); + + if ((flags & GPIO_OPEN_DRAIN) != 0U) { + otyper |= (1 << pin_num); + } else { + otyper &= ~(1 << pin_num); + } + WRITE_REG(p->OTYPER, otyper); + + if ((flags & GPIO_PULL_UP) != 0U) { + pupdr &= ~(0x3 << (pin_num * 2)); + pupdr |= (0x1 << (pin_num * 2)); + } else if ((flags & GPIO_PULL_DOWN) != 0U) { + pupdr &= ~(0x3 << (pin_num * 2)); + pupdr |= (0x2 << (pin_num * 2)); + } else { + pupdr &= ~(0x3 << (pin_num * 2)); + } + + WRITE_REG(p->PUPDR, pupdr); + + return 0; +} + +int stm32f769_gpio_configure_af(struct device *dev, uint32_t pin, uint32_t flags) +{ +// const struct gpio_stm32f769_config *config = port->config; + GPIO_TypeDef *p = NULL; + if (dev == NULL) { + uint32_t port_idx = STM32F769_PORT_GET(pin); + p = stm32f769_get_port(port_idx); + } else { + p = dev->devptr; + } + + uint32_t pin_num = pin & 0xf; + uint32_t moder = READ_REG(p->MODER); + uint32_t ospeedr = READ_REG(p->OSPEEDR); + uint32_t pupdr = READ_REG(p->PUPDR); + uint32_t otyper = READ_REG(p->OTYPER); + + moder &= ~((0x3) << (pin_num * 2)); + moder |= ((0x2) << (pin_num * 2)); + WRITE_REG(p->MODER, moder); + + // Low speed + ospeedr &= ~((0x3) << (pin_num * 2)); + WRITE_REG(p->OSPEEDR, ospeedr); + + if ((flags & GPIO_OPEN_DRAIN) != 0U) { + otyper |= (1 << pin_num); + } else { + otyper &= ~(1 << pin_num); + } + WRITE_REG(p->OTYPER, otyper); + + if ((flags & GPIO_PULL_UP) != 0U) { + pupdr &= ~(0x3 << (pin_num * 2)); + pupdr |= (0x1 << (pin_num * 2)); + } else if ((flags & GPIO_PULL_DOWN) != 0U) { + pupdr &= ~(0x3 << (pin_num * 2)); + pupdr |= (0x2 << (pin_num * 2)); + } else { + pupdr &= ~(0x3 << (pin_num * 2)); + } + + WRITE_REG(p->PUPDR, pupdr); + + return 0; +} + +int stm32f769_gpio_configure(struct device *dev, uint32_t pin, uint32_t flags) +{ +// const struct gpio_stm32f769_config *config = port->config; + GPIO_TypeDef *p = NULL; + if (dev == NULL) { + uint32_t port_idx = STM32F769_PORT_GET(pin); + p = stm32f769_get_port(port_idx); + } else { + p = dev->devptr; + } + + uint32_t pin_num = pin & 0xf; + uint32_t moder = READ_REG(p->MODER); + uint32_t ospeedr = READ_REG(p->OSPEEDR); + uint32_t pupdr = READ_REG(p->PUPDR); + uint32_t otyper = READ_REG(p->OTYPER); + + if ((flags & GPIO_OUTPUT) != 0U) { + // GPIO mode + moder &= ~((0x3) << (pin_num * 2)); + moder |= (0x01 << (pin_num * 2)); + WRITE_REG(p->MODER, moder); + + // Low speed + ospeedr &= ~((0x3) << (pin_num * 2)); + WRITE_REG(p->OSPEEDR, ospeedr); + + if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { + WRITE_REG(p->BSRR, BIT(pin_num)); + } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) { + WRITE_REG(p->BSRR, BIT(pin_num + 16)); + } + } else if ((flags & GPIO_INPUT) != 0U) { + // GPIO mode + moder &= ~((0x3) << (pin_num * 2)); + WRITE_REG(p->MODER, moder); + + // Low speed + ospeedr &= ~((0x3) << (pin_num * 2)); + WRITE_REG(p->OSPEEDR, ospeedr); + } else { // set mode ANALOG + // GPIO mode + moder |= ((0x3) << (pin_num * 2)); + WRITE_REG(p->MODER, moder); + + // Low speed + ospeedr &= ~((0x3) << (pin_num * 2)); + WRITE_REG(p->OSPEEDR, ospeedr); + } + + if ((flags & GPIO_OPEN_DRAIN) != 0U) { + otyper |= (1 << pin_num); + } else { + otyper &= ~(1 << pin_num); + } + WRITE_REG(p->OTYPER, otyper); + + if ((flags & GPIO_PULL_UP) != 0U) { + pupdr &= ~(0x3 << (pin_num * 2)); + pupdr |= (0x1 << (pin_num * 2)); + } else if ((flags & GPIO_PULL_DOWN) != 0U) { + pupdr &= ~(0x3 << (pin_num * 2)); + pupdr |= (0x2 << (pin_num * 2)); + } else { + pupdr &= ~(0x3 << (pin_num * 2)); + } + + WRITE_REG(p->PUPDR, pupdr); + + return 0; +} + +int stm32f769_gpio_init(struct device *dev) +{ + uint32_t clkid = 0; + switch ((uint32_t)dev->devptr) { + case GPIOA_BASE: + clkid = STM32F769_CLOCK_GPIOA; + break; + case GPIOB_BASE: + clkid = STM32F769_CLOCK_GPIOB; + break; + case GPIOC_BASE: + clkid = STM32F769_CLOCK_GPIOC; + break; + case GPIOD_BASE: + clkid = STM32F769_CLOCK_GPIOD; + break; + case GPIOE_BASE: + clkid = STM32F769_CLOCK_GPIOE; + break; + case GPIOF_BASE: + clkid = STM32F769_CLOCK_GPIOF; + break; + case GPIOG_BASE: + clkid = STM32F769_CLOCK_GPIOG; + break; + case GPIOH_BASE: + clkid = STM32F769_CLOCK_GPIOH; + break; + case GPIOI_BASE: + clkid = STM32F769_CLOCK_GPIOI; + break; + case GPIOJ_BASE: + clkid = STM32F769_CLOCK_GPIOJ; + break; + case GPIOK_BASE: + clkid = STM32F769_CLOCK_GPIOK; + break; + default: + return -1; + } + + stm32f769_clock_control_on(clkid); + + return 0; +} + +int stm32f769_gpio_read(struct device *dev, uint32_t pin) { + GPIO_TypeDef *p = dev->devptr; + uint32_t state = READ_REG(p->IDR); + if (state & BIT(pin)) { + return 1; + } + return 0; +} + +void stm32f769_gpio_write(struct device *dev, uint32_t pin, int val) { + GPIO_TypeDef *p = dev->devptr; + if (val == 0) { + WRITE_REG(p->BSRR, BIT(pin + 16)); + } else { + WRITE_REG(p->BSRR, BIT(pin)); + } +} diff --git a/os/drivers/gpio/stm32f769_gpio.h b/os/drivers/gpio/stm32f769_gpio.h new file mode 100644 index 00000000..d009921c --- /dev/null +++ b/os/drivers/gpio/stm32f769_gpio.h @@ -0,0 +1,13 @@ +#ifndef __STM32F769_GPIO_H__ +#define __STM32F769_GPIO_H__ + +#include <stdint.h> + +int stm32f769_gpio_configure(struct device *dev, uint32_t pin, uint32_t flags); +int stm32f769_gpio_configure_analog(struct device *dev, uint32_t pin, uint32_t flags); +int stm32f769_gpio_configure_af(struct device *dev, uint32_t pin, uint32_t flags); +int stm32f769_gpio_init(struct device *dev); +int stm32f769_gpio_read(struct device *dev, uint32_t pin); +void stm32f769_gpio_write(struct device *dev, uint32_t pin, int val); + +#endif/*__STM32F769_GPIO_H__*/ diff --git a/os/drivers/memory/stm32f7_mpu.c b/os/drivers/memory/stm32f7_mpu.c index dbca7027..fc45714b 100644 --- a/os/drivers/memory/stm32f7_mpu.c +++ b/os/drivers/memory/stm32f7_mpu.c @@ -1,8 +1,10 @@ #include <stdint.h> #include "stm32f7_mpu.h" +#include <arch/aarch32/armv7e_m/stm32f7/stm32f769xx.h> +#include <arch/sys_io.h> +#include <arch/aarch32/armv7e_m/stm32f769/cortex.h> #include <drivers/include/device.h> -#include <arch/aarch32/stm32f7/stm32f769xx.h> -#include <arch/aarch32/core_cm7.h> +#include <arch/aarch32/armv7e_m/cmsis/core_cm7.h> static void __mpu_disable(void) { @@ -36,7 +38,7 @@ int stm32f7_mpu_init(struct device *dev) { MPU->RNR = MPU_REGION_NUMBER0; /* Disable the Region */ - CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + MODIFY_REG(MPU->RASR, MPU_RASR_ENABLE_Msk, 0); /* Apply configuration */ MPU->RBAR = 0; // Base addr diff --git a/os/drivers/pinctrl/pinctrl.h b/os/drivers/pinctrl/pinctrl.h new file mode 100644 index 00000000..a23b5b19 --- /dev/null +++ b/os/drivers/pinctrl/pinctrl.h @@ -0,0 +1,6 @@ +#ifndef __PINCTRL_H__ +#define __PINCTRL_H__ + +void pinctrl_configure_pin(uint32_t pin); + +#endif/*__PINCTRL_H__*/ diff --git a/os/drivers/pinctrl/stm32f769_pinctrl.c b/os/drivers/pinctrl/stm32f769_pinctrl.c new file mode 100644 index 00000000..98b975f6 --- /dev/null +++ b/os/drivers/pinctrl/stm32f769_pinctrl.c @@ -0,0 +1,90 @@ +#include <arch/sys_io.h> +#include <arch/aarch32/armv7e_m/stm32f7/stm32f769xx.h> +#include <drivers/clock/stm32f769_clocks.h> +#include <drivers/clock/stm32f769_clock_control.h> +#include <drivers/gpio/stm32f769_gpio.h> + +#include <stddef.h> +#include "stm32f769_pinctrl.h" + +static const GPIO_TypeDef *stm32f769_port_addrs[] = { + GPIOA, + GPIOB, + GPIOC, + GPIOD, + GPIOE, + GPIOF, + GPIOG, + GPIOH, + GPIOI, + GPIOJ, + GPIOK, +}; + +static const uint16_t stm32f769_port_clkids[] = { + STM32F769_CLOCK_GPIOA, + STM32F769_CLOCK_GPIOB, + STM32F769_CLOCK_GPIOC, + STM32F769_CLOCK_GPIOD, + STM32F769_CLOCK_GPIOE, + STM32F769_CLOCK_GPIOF, + STM32F769_CLOCK_GPIOG, + STM32F769_CLOCK_GPIOH, + STM32F769_CLOCK_GPIOI, + STM32F769_CLOCK_GPIOJ, + STM32F769_CLOCK_GPIOK, +}; + +GPIO_TypeDef *stm32f769_get_port(unsigned int port_idx) { + GPIO_TypeDef *p = stm32f769_port_addrs[port_idx]; + return p; +} + +uint16_t stm32f769_get_port_clkid(unsigned int port_idx) { + return stm32f769_port_clkids[port_idx]; +} + +void stm32f769_pinctrl_configure_pin(uint32_t pin) +{ + uint8_t port_idx; + uint32_t port; + uint32_t pin_num; + uint32_t af; + uint16_t clkid; + //uint16_t strength; + + port_idx = STM32F769_PORT_GET(pin); + GPIO_TypeDef *p = stm32f769_get_port(port_idx); + + clkid = stm32f769_get_port_clkid(port_idx); + + pin_num = STM32F769_PIN_GET(pin); + af = STM32F769_AF_GET(pin); + + stm32f769_clock_control_on(clkid); + + if (af != STM32F769_ANALOG) { + stm32f769_gpio_configure_af(NULL, pin, pin); + if (pin_num < 8) { + MODIFY_REG(p->AFR[0], (0xf << (pin_num * 4)), (af << (pin_num * 4))); + } else { + MODIFY_REG(p->AFR[1], (0xf << ((pin_num - 8) * 4)), (af << ((pin_num - 8) * 4))); + } + } else { + // set mode ANALOG + stm32f769_gpio_configure_analog(NULL, pin, pin); + } +} + +/* int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, */ +/* uintptr_t reg) */ +/* { */ +/* ARG_UNUSED(reg); */ + +/* for (uint8_t i = 0U; i < pin_cnt; i++) { */ +/* pinctrl_configure_pin(pins[i]); */ +/* } */ + +/* return 0; */ +/* } */ + diff --git a/os/drivers/pinctrl/stm32f769_pinctrl.h b/os/drivers/pinctrl/stm32f769_pinctrl.h new file mode 100644 index 00000000..85a6cb60 --- /dev/null +++ b/os/drivers/pinctrl/stm32f769_pinctrl.h @@ -0,0 +1,69 @@ +#ifndef __DT_BINDINGS_PINCTRL_STM32F769_AF_H__ +#define __DT_BINDINGS_PINCTRL_STM32F769_AF_H__ + +#define STM32F769_AF0 0U +#define STM32F769_AF1 1U +#define STM32F769_AF2 2U +#define STM32F769_AF3 3U +#define STM32F769_AF4 4U +#define STM32F769_AF5 5U +#define STM32F769_AF6 6U +#define STM32F769_AF7 7U +#define STM32F769_AF8 8U +#define STM32F769_AF9 9U +#define STM32F769_AF10 10U +#define STM32F769_AF11 11U +#define STM32F769_AF12 12U +#define STM32F769_AF13 13U +#define STM32F769_AF14 14U +#define STM32F769_AF15 15U +#define STM32F769_ANALOG 16U + +#define STM32F769_PIN_MSK 0xFU +#define STM32F769_PIN_POS 0U +#define STM32F769_PORT_MSK 0xFU +#define STM32F769_PORT_POS 4U +#define STM32F769_AF_MSK 0x1FU +#define STM32F769_AF_POS 8U + +#define STM32F769_PORTA 0 +#define STM32F769_PORTB 1 +#define STM32F769_PORTC 2 +#define STM32F769_PORTD 3 +#define STM32F769_PORTE 4 +#define STM32F769_PORTF 5 +#define STM32F769_PORTG 6 +#define STM32F769_PORTH 7 +#define STM32F769_PORTI 8 +#define STM32F769_PORTJ 9 +#define STM32F769_PORTK 10 + +#define STM32F769_PORT_GET(pinmux) \ + (((pinmux) >> STM32F769_PORT_POS) & STM32F769_PORT_MSK) + +#define STM32F769_PIN_GET(pinmux) \ + (((pinmux) >> STM32F769_PIN_POS) & STM32F769_PIN_MSK) + +#define STM32F769_AF_GET(pinmux) \ + (((pinmux) >> STM32F769_AF_POS) & STM32F769_AF_MSK) + +/** + * - 0..3: pin + * - 4..7: port + * - 8..13: af + * + * port: Port ('A'..'K') + * pin: Pin (0..15) + * af: Alternate function (ANALOG, AFx, x=0..15) + */ + +#define STM32F769_PINMUX_AF(port, pin, af) \ + ((((port) & STM32F769_PORT_MSK) << STM32F769_PORT_POS) | \ + (((pin) & STM32F769_PIN_MSK) << STM32F769_PIN_POS) | \ + (((STM32F769_ ## af) & STM32F769_AF_MSK) << STM32F769_AF_POS)) + +void stm32f769_pinctrl_configure_pin(uint32_t pin); +GPIO_TypeDef *stm32f769_get_port(unsigned int port_idx); +uint16_t stm32f769_get_port_clkid(unsigned int port_idx); + +#endif/*__DT_BINDINGS_PINCTRL_STM32F769_AF_H_ */ diff --git a/os/drivers/uart/stm32f7_uart.c b/os/drivers/uart/stm32f7_uart.c new file mode 100644 index 00000000..76f67ae9 --- /dev/null +++ b/os/drivers/uart/stm32f7_uart.c @@ -0,0 +1,168 @@ +#include <arch/aarch32/armv7e_m/stm32f7/stm32f769xx.h> +#include <arch/sys_io.h> + +#include <drivers/clock/stm32f769_clocks.h> +#include <drivers/clock/stm32f769_clock_control.h> + +#include <string.h> + +#include "uart.h" +#include "stm32f7_uart.h" + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ + +inline static void __uart_disable(struct device *dev) { + USART_TypeDef *p = dev->devptr; + p->CR1 &= ~USART_CR1_UE; +} + +inline static void __uart_enable(struct device *dev) { + USART_TypeDef *p = dev->devptr; + p->CR1 |= USART_CR1_UE; +} + +int stm32f7_uart_init(struct device *dev) { + USART_TypeDef *p = dev->devptr; + stm32f7_uart_deinit(dev); + + uint32_t clk_rate = 0; + uint32_t parity = 0; + uint32_t stop_bits = 0; + uint32_t word_length = 0; + + struct uart_data *uart = (struct uart_data *)dev->data; + + switch ((uint32_t)p) { + case USART1_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_USART1, &clk_rate); + break; + case USART2_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_USART2, &clk_rate); + break; + case USART3_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_USART3, &clk_rate); + break; + case UART4_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_UART4, &clk_rate); + break; + case UART5_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_UART5, &clk_rate); + break; + case USART6_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_USART6, &clk_rate); + break; + case UART7_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_UART7, &clk_rate); + break; + case UART8_BASE: + stm32f769_clock_control_get_rate(STM32F769_CLOCK_UART8, &clk_rate); + break; + default: + return -1; + } + + switch (uart->data_bits) { + case UART_CFG_DATA_BITS_7: + word_length = USART_CR1_M1; + break; + case UART_CFG_DATA_BITS_8: + word_length = 0; + break; + case UART_CFG_DATA_BITS_9: + word_length = USART_CR1_M0; + break; + case UART_CFG_DATA_BITS_5: + case UART_CFG_DATA_BITS_6: + default: + return -1; + } + + switch (uart->parity) { + case UART_CFG_PARITY_NONE: + parity = 0; + break; + case UART_CFG_PARITY_ODD: + parity = USART_CR1_PCE; + break; + case UART_CFG_PARITY_EVEN: + parity = (USART_CR1_PCE | USART_CR1_PS); + break; + case UART_CFG_PARITY_MARK: + case UART_CFG_PARITY_SPACE: + default: + return -1; + } + + switch (uart->stop_bits) { + case UART_CFG_STOP_BITS_0_5: + stop_bits = USART_CR2_STOP_0; + break; + case UART_CFG_STOP_BITS_1: + stop_bits = 0; + break; + case UART_CFG_STOP_BITS_1_5: + stop_bits = (USART_CR2_STOP_0 | USART_CR2_STOP_1); + break; + case UART_CFG_STOP_BITS_2: + stop_bits = USART_CR2_STOP_1; + break; + default: + return -1; + } + + uint32_t cr1 = word_length | parity | USART_CR1_TE | USART_CR1_RE; + WRITE_REG(p->CR1, cr1); + cr1 = READ_REG(p->CR1); + + uint32_t cr2 = stop_bits; + WRITE_REG(p->CR2, cr2); + cr2 = READ_REG(p->CR2); + + uint32_t cr3 = 0; + WRITE_REG(p->CR3, cr3); + cr3 = READ_REG(p->CR3); + + uint32_t div = (clk_rate + ((uart->baudrate)/2U)) / (uart->baudrate); + if ((div >= UART_BRR_MIN) && (div <= UART_BRR_MAX)) { + p->BRR = (uint16_t)div; + } else { + return -1; + } + + CLEAR_BIT(p->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(p->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __uart_enable(dev); + return 0; +} + +int stm32f7_uart_deinit(struct device *dev) { + __uart_disable(dev); + USART_TypeDef *p = dev->devptr; + p->CR1 = 0x0U; + p->CR2 = 0x0U; + p->CR3 = 0x0U; + return 0; +} + +void stm32f7_uart_poll_out8(const struct device *dev, unsigned char ch) +{ + USART_TypeDef *p = dev->devptr; + + while ((p->ISR & USART_ISR_TXE) == 0) { + } + + p->TDR = ch; +} + +void stm32f7_uart_tx_buffer(const struct device *dev, char *buffer, unsigned int len) { + unsigned int i = 0; + for (;i < len; i++) { + stm32f7_uart_poll_out8(dev, buffer[i]); + } +} + +void stm32f7_uart_tx(const struct device *dev, char *buffer) { + stm32f7_uart_tx_buffer(dev, buffer, strlen(buffer)); +} diff --git a/os/drivers/uart/stm32f7_uart.h b/os/drivers/uart/stm32f7_uart.h new file mode 100644 index 00000000..224f20ea --- /dev/null +++ b/os/drivers/uart/stm32f7_uart.h @@ -0,0 +1,12 @@ +#ifndef __STM32F7_UART_H__ +#define __STM32F7_UART_H__ + +#include <drivers/include/device.h> + +int stm32f7_uart_init(struct device *dev); +int stm32f7_uart_deinit(struct device *dev); +void stm32f7_uart_poll_out8(const struct device *dev, unsigned char ch); +void stm32f7_uart_tx_buffer(const struct device *dev, char *buffer, unsigned int len); +void stm32f7_uart_tx(const struct device *dev, char *buffer); + +#endif/*__STM32F7_UART_H__*/ diff --git a/os/drivers/uart/uart.h b/os/drivers/uart/uart.h new file mode 100644 index 00000000..afde5315 --- /dev/null +++ b/os/drivers/uart/uart.h @@ -0,0 +1,37 @@ +#ifndef __UART_H__ +#define __UART_H__ + +enum uart_config_parity { + UART_CFG_PARITY_NONE, /**< No parity */ + UART_CFG_PARITY_ODD, /**< Odd parity */ + UART_CFG_PARITY_EVEN, /**< Even parity */ + UART_CFG_PARITY_MARK, /**< Mark parity */ + UART_CFG_PARITY_SPACE, /**< Space parity */ +}; + +/** @brief Number of stop bits. */ +enum uart_config_stop_bits { + UART_CFG_STOP_BITS_0_5, /**< 0.5 stop bit */ + UART_CFG_STOP_BITS_1, /**< 1 stop bit */ + UART_CFG_STOP_BITS_1_5, /**< 1.5 stop bits */ + UART_CFG_STOP_BITS_2, /**< 2 stop bits */ +}; + +/** @brief Number of data bits. */ +enum uart_config_data_bits { + UART_CFG_DATA_BITS_5, /**< 5 data bits */ + UART_CFG_DATA_BITS_6, /**< 6 data bits */ + UART_CFG_DATA_BITS_7, /**< 7 data bits */ + UART_CFG_DATA_BITS_8, /**< 8 data bits */ + UART_CFG_DATA_BITS_9, /**< 9 data bits */ +}; + +struct uart_data { + struct device *dev; + int baudrate; + enum uart_config_parity parity; + enum uart_config_stop_bits stop_bits; + enum uart_config_data_bits data_bits; +}; + +#endif/*__UART_H__*/ |