diff options
Diffstat (limited to 'os/boot/pc')
49 files changed, 14759 insertions, 1835 deletions
diff --git a/os/boot/pc/ahci.h b/os/boot/pc/ahci.h new file mode 100644 index 00000000..e96b16eb --- /dev/null +++ b/os/boot/pc/ahci.h @@ -0,0 +1,275 @@ +/* + * advanced host controller interface (sata) + * © 2007 coraid, inc + */ + +/* ata errors */ +enum { + Emed = 1<<0, /* media error */ + Enm = 1<<1, /* no media */ + Eabrt = 1<<2, /* abort */ + Emcr = 1<<3, /* media change request */ + Eidnf = 1<<4, /* no user-accessible address */ + Emc = 1<<5, /* media change */ + Eunc = 1<<6, /* data error */ + Ewp = 1<<6, /* write protect */ + Eicrc = 1<<7, /* interface crc error */ + + Efatal = Eidnf|Eicrc, /* must sw reset */ +}; + +/* ata status */ +enum { + ASerr = 1<<0, /* error */ + ASdrq = 1<<3, /* request */ + ASdf = 1<<5, /* fault */ + ASdrdy = 1<<6, /* ready */ + ASbsy = 1<<7, /* busy */ + + ASobs = 1<<1|1<<2|1<<4, +}; + +/* pci configuration */ +enum { + Abar = 5, +}; + +/* + * ahci memory configuration + * + * 0000-0023 generic host control + * 0024-009f reserved + * 00a0-00ff vendor specific. + * 0100-017f port 0 + * ... + * 1080-1100 port 31 + */ + +/* cap bits: supported features */ +enum { + Hs64a = 1<<31, /* 64-bit addressing */ + Hsncq = 1<<30, /* ncq */ + Hssntf = 1<<29, /* snotification reg. */ + Hsmps = 1<<28, /* mech pres switch */ + Hsss = 1<<27, /* staggered spinup */ + Hsalp = 1<<26, /* aggressive link pm */ + Hsal = 1<<25, /* activity led */ + Hsclo = 1<<24, /* command-list override */ + Hiss = 1<<20, /* for interface speed */ +// Hsnzo = 1<<19, + Hsam = 1<<18, /* ahci-mode only */ + Hspm = 1<<17, /* port multiplier */ +// Hfbss = 1<<16, + Hpmb = 1<<15, /* multiple-block pio */ + Hssc = 1<<14, /* slumber state */ + Hpsc = 1<<13, /* partial-slumber state */ + Hncs = 1<<8, /* n command slots */ + Hcccs = 1<<7, /* coal */ + Hems = 1<<6, /* enclosure mgmt. */ + Hsxs = 1<<5, /* external sata */ + Hnp = 1<<0, /* n ports */ +}; + +/* ghc bits */ +enum { + Hae = 1<<31, /* enable ahci */ + Hie = 1<<1, /* " interrupts */ + Hhr = 1<<0, /* hba reset */ +}; + +typedef struct { + ulong cap; + ulong ghc; + ulong isr; + ulong pi; /* ports implemented */ + ulong ver; + ulong ccc; /* coaleasing control */ + ulong cccports; + ulong emloc; + ulong emctl; +} Ahba; + +enum { + Acpds = 1<<31, /* cold port detect status */ + Atfes = 1<<30, /* task file error status */ + Ahbfs = 1<<29, /* hba fatal */ + Ahbds = 1<<28, /* hba error (parity error) */ + Aifs = 1<<27, /* interface fatal §6.1.2 */ + Ainfs = 1<<26, /* interface error (recovered) */ + Aofs = 1<<24, /* too many bytes from disk */ + Aipms = 1<<23, /* incorrect prt mul status */ + Aprcs = 1<<22, /* PhyRdy change status Pxserr.diag.n */ + Adpms = 1<<7, /* mechanical presence status */ + Apcs = 1<<6, /* port connect diag.x */ + Adps = 1<<5, /* descriptor processed */ + Aufs = 1<<4, /* unknown fis diag.f */ + Asdbs = 1<<3, /* set device bits fis received w/ i bit set */ + Adss = 1<<2, /* dma setup */ + Apio = 1<<1, /* pio setup fis */ + Adhrs = 1<<0, /* device to host register fis */ + + IEM = Acpds|Atfes|Ahbds|Ahbfs|Ahbds|Aifs|Ainfs|Aprcs|Apcs|Adps| + Aufs|Asdbs|Adss|Adhrs, + Ifatal = Atfes|Ahbfs|Ahbds|Aifs, +}; + +/* serror bits */ +enum { + SerrX = 1<<26, /* exchanged */ + SerrF = 1<<25, /* unknown fis */ + SerrT = 1<<24, /* transition error */ + SerrS = 1<<23, /* link sequence */ + SerrH = 1<<22, /* handshake */ + SerrC = 1<<21, /* crc */ + SerrD = 1<<20, /* not used by ahci */ + SerrB = 1<<19, /* 10-tp-8 decode */ + SerrW = 1<<18, /* comm wake */ + SerrI = 1<<17, /* phy internal */ + SerrN = 1<<16, /* phyrdy change */ + + ErrE = 1<<11, /* internal */ + ErrP = 1<<10, /* ata protocol violation */ + ErrC = 1<<9, /* communication */ + ErrT = 1<<8, /* transient */ + ErrM = 1<<1, /* recoverd comm */ + ErrI = 1<<0, /* recovered data integrety */ + + ErrAll = ErrE|ErrP|ErrC|ErrT|ErrM|ErrI, + SerrAll = SerrX|SerrF|SerrT|SerrS|SerrH|SerrC|SerrD|SerrB|SerrW| + SerrI|SerrN|ErrAll, + SerrBad = 0x7f<<19, +}; + +/* cmd register bits */ +enum { + Aicc = 1<<28, /* interface communcations control. 4 bits */ + Aasp = 1<<27, /* agressive slumber & partial sleep */ + Aalpe = 1<<26, /* agressive link pm enable */ + Adlae = 1<<25, /* drive led on atapi */ + Aatapi = 1<<24, /* device is atapi */ + Aesp = 1<<21, /* external sata port */ + Acpd = 1<<20, /* cold presence detect */ + Ampsp = 1<<19, /* mechanical pres. */ + Ahpcp = 1<<18, /* hot plug capable */ + Apma = 1<<17, /* pm attached */ + Acps = 1<<16, /* cold presence state */ + Acr = 1<<15, /* cmdlist running */ + Afr = 1<<14, /* fis running */ + Ampss = 1<<13, /* mechanical presence switch state */ + Accs = 1<<8, /* current command slot 12:08 */ + Afre = 1<<4, /* fis enable receive */ + Aclo = 1<<3, /* command list override */ + Apod = 1<<2, /* power on dev (requires cold-pres. detect) */ + Asud = 1<<1, /* spin-up device; requires ss capability */ + Ast = 1<<0, /* start */ + + Arun = Ast|Acr|Afre|Afr, +}; + +/* ctl register bits */ +enum { + Aipm = 1<<8, /* interface power mgmt. 3=off */ + Aspd = 1<<4, + Adet = 1<<0, /* device detection */ +}; + +#define sstatus scr0 +#define sctl scr2 +#define serror scr1 +#define sactive scr3 + +typedef struct { + ulong list; /* PxCLB must be 1kb aligned. */ + ulong listhi; + ulong fis; /* 256-byte aligned */ + ulong fishi; + ulong isr; + ulong ie; /* interrupt enable */ + ulong cmd; + ulong res1; + ulong task; + ulong sig; + ulong scr0; + ulong scr2; + ulong scr1; + ulong scr3; + ulong ci; /* command issue */ + ulong ntf; + uchar res2[8]; + ulong vendor; +} Aport; + +/* in host's memory; not memory mapped */ +typedef struct { + uchar *base; + uchar *d; + uchar *p; + uchar *r; + uchar *u; + ulong *devicebits; +} Afis; + +enum { + Lprdtl = 1<<16, /* physical region descriptor table len */ + Lpmp = 1<<12, /* port multiplier port */ + Lclear = 1<<10, /* clear busy on R_OK */ + Lbist = 1<<9, + Lreset = 1<<8, + Lpref = 1<<7, /* prefetchable */ + Lwrite = 1<<6, + Latapi = 1<<5, + Lcfl = 1<<0, /* command fis length in double words */ +}; + +/* in hosts memory; memory mapped */ +typedef struct { + ulong flags; + ulong len; + ulong ctab; + ulong ctabhi; + uchar reserved[16]; +} Alist; + +typedef struct { + ulong dba; + ulong dbahi; + ulong pad; + ulong count; +} Aprdt; + +typedef struct { + uchar cfis[0x40]; + uchar atapi[0x10]; + uchar pad[0x30]; + Aprdt prdt; +} Actab; + +enum { + Ferror = 1, + Fdone = 2, +}; + +enum { + Dllba = 1, + Dsmart = 1<<1, + Dpower = 1<<2, + Dnop = 1<<3, + Datapi = 1<<4, + Datapi16= 1<<5, +}; + +typedef struct { +// QLock; +// Rendez; + uchar flag; + uchar feat; + uchar smart; + Afis fis; + Alist *list; + Actab *ctab; +} Aportm; + +typedef struct { + Aport *p; + Aportm *m; +} Aportc; diff --git a/os/boot/pc/aoe.h b/os/boot/pc/aoe.h new file mode 100644 index 00000000..b06a1a92 --- /dev/null +++ b/os/boot/pc/aoe.h @@ -0,0 +1,76 @@ +/* + * ATA-over-Ethernet + */ +enum { + ACata, + ACconfig, +}; + +enum { + AQCread, + AQCtest, + AQCprefix, + AQCset, + AQCfset, +}; + +enum { + AEcmd = 1, + AEarg, + AEdev, + AEcfg, + AEver, +}; + +enum { + Aoetype = 0x88a2, + Aoever = 1, + + AFerr = 1<<2, + AFrsp = 1<<3, + + AAFwrite= 1, + AAFext = 1<<6, +}; + +enum { + Crd = 0x20, + Crdext = 0x24, + Cwr = 0x30, + Cwrext = 0x34, + Cid = 0xec, +}; + +typedef struct { + uchar dst[Eaddrlen]; + uchar src[Eaddrlen]; + uchar type[2]; + uchar verflag; + uchar error; + uchar major[2]; + uchar minor; + uchar cmd; + uchar tag[4]; +} Aoehdr; + +typedef struct { + Aoehdr; + uchar aflag; + uchar errfeat; + uchar scnt; + uchar cmdstat; + uchar lba[6]; + uchar res[2]; +} Aoeata; + +typedef struct { + Aoehdr; + uchar bufcnt[2]; + uchar fwver[2]; + uchar scnt; + uchar verccmd; + uchar cslen[2]; +} Aoeqc; + +extern char Echange[]; +extern char Enotup[]; diff --git a/os/boot/pc/bcom.c b/os/boot/pc/bcom.c index 62a50a10..73925bf7 100644 --- a/os/boot/pc/bcom.c +++ b/os/boot/pc/bcom.c @@ -1,3 +1,6 @@ +/* + * ld - DOS boot loader of Plan 9 + */ #include "u.h" #include "lib.h" #include "mem.h" diff --git a/os/boot/pc/bootp.c b/os/boot/pc/bootp.c index 64df7e14..92caadf2 100644 --- a/os/boot/pc/bootp.c +++ b/os/boot/pc/bootp.c @@ -7,6 +7,8 @@ #include "ip.h" +extern int debugload; + uchar broadcast[Eaddrlen] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }; @@ -292,15 +294,15 @@ udprecv(int ctlrno, Netaddr *a, void *data, int dlen) if(a->port != 0 && nhgets(h->udpsport) != a->port) { if(debug) - print("udpport %ux %ux\n", + print("udpport %ux not %ux\n", nhgets(h->udpsport), a->port); continue; } addr = nhgetl(h->udpsrc); - if(a->ip != Bcastip && addr != a->ip) { + if(a->ip != Bcastip && a->ip != addr) { if(debug) - print("bad ip\n"); + print("bad ip %lux not %lux\n", addr, a->ip); continue; } @@ -441,6 +443,8 @@ bootpopen(int ctlrno, char *file, Bootp *rep, int dotftpopen) uchar *ea; char name[128], *filename, *sysname; + if (debugload) + print("bootpopen: ether%d!%s...", ctlrno, file); if((ea = etheraddr(ctlrno)) == 0){ print("invalid ctlrno %d\n", ctlrno); return -1; @@ -620,7 +624,8 @@ pxewalk(File* f, char* name) return 0; ini = pxether[f->fs->dev].ini; - snprint(ini, INIPATHLEN, "/cfg/pxe/%E", rep.chaddr); + /* use our mac address instead of relying on a bootp answer */ + snprint(ini, INIPATHLEN, "/cfg/pxe/%E", (uchar *)myaddr.ea); f->path = ini; return 1; @@ -637,6 +642,8 @@ pxegetfspart(int ctlrno, char* part, int) return nil; if(ctlrno >= MaxEther) return nil; + if(iniread && getconf("*pxeini") != nil) + return nil; pxether[ctlrno].fs.dev = ctlrno; pxether[ctlrno].fs.diskread = pxediskread; diff --git a/os/boot/pc/cis.c b/os/boot/pc/cis.c new file mode 100644 index 00000000..5c28506b --- /dev/null +++ b/os/boot/pc/cis.c @@ -0,0 +1,539 @@ +#include "u.h" +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "error.h" +#include "io.h" + +enum{ + Linktarget = 0x13, +}; + +/* + * read and crack the card information structure enough to set + * important parameters like power + */ +/* cis memory walking */ +typedef struct Cisdat { + uchar *cisbase; + int cispos; + int cisskip; + int cislen; +} Cisdat; + +static void tcfig(PCMslot*, Cisdat*, int); +static void tentry(PCMslot*, Cisdat*, int); +static void tvers1(PCMslot*, Cisdat*, int); +static void tlonglnkmfc(PCMslot*, Cisdat*, int); + +static int +readc(Cisdat *cis, uchar *x) +{ + if(cis->cispos >= cis->cislen) + return 0; + *x = cis->cisbase[cis->cisskip*cis->cispos]; + cis->cispos++; + return 1; +} + +static int +xcistuple(int slotno, int tuple, int subtuple, void *v, int nv, int attr) +{ + PCMmap *m; + Cisdat cis; + int i, l; + uchar *p; + uchar type, link, n, c; + int this, subtype; + + m = pcmmap(slotno, 0, 0, attr); + if(m == 0) + return -1; + + cis.cisbase = KADDR(m->isa); + cis.cispos = 0; + cis.cisskip = attr ? 2 : 1; + cis.cislen = m->len; + + /* loop through all the tuples */ + for(i = 0; i < 1000; i++){ + this = cis.cispos; + if(readc(&cis, &type) != 1) + break; + if(type == 0xFF) + break; + if(readc(&cis, &link) != 1) + break; + if(link == 0xFF) + break; + + n = link; + if(link > 1 && subtuple != -1){ + if(readc(&cis, &c) != 1) + break; + subtype = c; + n--; + }else + subtype = -1; + + if(type == tuple && subtype == subtuple){ + p = v; + for(l=0; l<nv && l<n; l++) + if(readc(&cis, p++) != 1) + break; + pcmunmap(slotno, m); + return nv; + } + cis.cispos = this + (2+link); + } + pcmunmap(slotno, m); + return -1; +} + +int +pcmcistuple(int slotno, int tuple, int subtuple, void *v, int nv) +{ + int n; + + /* try attribute space, then memory */ + if((n = xcistuple(slotno, tuple, subtuple, v, nv, 1)) >= 0) + return n; + return xcistuple(slotno, tuple, subtuple, v, nv, 0); +} + +void +pcmcisread(PCMslot *pp) +{ + int this; + Cisdat cis; + PCMmap *m; + uchar type, link; + + memset(pp->ctab, 0, sizeof(pp->ctab)); + pp->ncfg = 0; + memset(pp->cfg, 0, sizeof(pp->cfg)); + pp->configed = 0; + pp->nctab = 0; + pp->verstr[0] = 0; + + /* + * Read all tuples in attribute space. + */ + m = pcmmap(pp->slotno, 0, 0, 1); + if(m == 0) + return; + + cis.cisbase = KADDR(m->isa); + cis.cispos = 0; + cis.cisskip = 2; + cis.cislen = m->len; + + /* loop through all the tuples */ + for(;;){ + this = cis.cispos; + if(readc(&cis, &type) != 1) + break; + if(type == 0xFF) + break; + if(readc(&cis, &link) != 1) + break; + + switch(type){ + default: + break; + case 6: + tlonglnkmfc(pp, &cis, type); + break; + case 0x15: + tvers1(pp, &cis, type); + break; + case 0x1A: + tcfig(pp, &cis, type); + break; + case 0x1B: + tentry(pp, &cis, type); + break; + } + + if(link == 0xFF) + break; + cis.cispos = this + (2+link); + } + pcmunmap(pp->slotno, m); +} + +static ulong +getlong(Cisdat *cis, int size) +{ + uchar c; + int i; + ulong x; + + x = 0; + for(i = 0; i < size; i++){ + if(readc(cis, &c) != 1) + break; + x |= c<<(i*8); + } + return x; +} + +static void +tcfig(PCMslot *pp, Cisdat *cis, int ) +{ + uchar size, rasize, rmsize; + uchar last; + + if(readc(cis, &size) != 1) + return; + rasize = (size&0x3) + 1; + rmsize = ((size>>2)&0xf) + 1; + if(readc(cis, &last) != 1) + return; + + if(pp->ncfg >= 8){ + print("tcfig: too many configuration registers\n"); + return; + } + + pp->cfg[pp->ncfg].caddr = getlong(cis, rasize); + pp->cfg[pp->ncfg].cpresent = getlong(cis, rmsize); + pp->ncfg++; +} + +static ulong vexp[8] = +{ + 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 +}; +static ulong vmant[16] = +{ + 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90, +}; + +static ulong +microvolt(Cisdat *cis) +{ + uchar c; + ulong microvolts; + ulong exp; + + if(readc(cis, &c) != 1) + return 0; + exp = vexp[c&0x7]; + microvolts = vmant[(c>>3)&0xf]*exp; + while(c & 0x80){ + if(readc(cis, &c) != 1) + return 0; + switch(c){ + case 0x7d: + break; /* high impedence when sleeping */ + case 0x7e: + case 0x7f: + microvolts = 0; /* no connection */ + break; + default: + exp /= 10; + microvolts += exp*(c&0x7f); + } + } + return microvolts; +} + +static ulong +nanoamps(Cisdat *cis) +{ + uchar c; + ulong nanoamps; + + if(readc(cis, &c) != 1) + return 0; + nanoamps = vexp[c&0x7]*vmant[(c>>3)&0xf]; + while(c & 0x80){ + if(readc(cis, &c) != 1) + return 0; + if(c == 0x7d || c == 0x7e || c == 0x7f) + nanoamps = 0; + } + return nanoamps; +} + +/* + * only nominal voltage (feature 1) is important for config, + * other features must read card to stay in sync. + */ +static ulong +power(Cisdat *cis) +{ + uchar feature; + ulong mv; + + mv = 0; + if(readc(cis, &feature) != 1) + return 0; + if(feature & 1) + mv = microvolt(cis); + if(feature & 2) + microvolt(cis); + if(feature & 4) + microvolt(cis); + if(feature & 8) + nanoamps(cis); + if(feature & 0x10) + nanoamps(cis); + if(feature & 0x20) + nanoamps(cis); + if(feature & 0x40) + nanoamps(cis); + return mv/1000000; +} + +static ulong mantissa[16] = +{ 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, }; + +static ulong exponent[8] = +{ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, }; + +static ulong +ttiming(Cisdat *cis, int scale) +{ + uchar unscaled; + ulong nanosecs; + + if(readc(cis, &unscaled) != 1) + return 0; + nanosecs = (mantissa[(unscaled>>3)&0xf]*exponent[unscaled&7])/10; + nanosecs = nanosecs * vexp[scale]; + return nanosecs; +} + +static void +timing(Cisdat *cis, PCMconftab *ct) +{ + uchar c, i; + + if(readc(cis, &c) != 1) + return; + i = c&0x3; + if(i != 3) + ct->maxwait = ttiming(cis, i); /* max wait */ + i = (c>>2)&0x7; + if(i != 7) + ct->readywait = ttiming(cis, i); /* max ready/busy wait */ + i = (c>>5)&0x7; + if(i != 7) + ct->otherwait = ttiming(cis, i); /* reserved wait */ +} + +static void +iospaces(Cisdat *cis, PCMconftab *ct) +{ + uchar c; + int i, nio; + + ct->nio = 0; + if(readc(cis, &c) != 1) + return; + + ct->bit16 = ((c>>5)&3) >= 2; + if(!(c & 0x80)){ + ct->io[0].start = 0; + ct->io[0].len = 1<<(c&0x1f); + ct->nio = 1; + return; + } + + if(readc(cis, &c) != 1) + return; + + /* + * For each of the range descriptions read the + * start address and the length (value is length-1). + */ + nio = (c&0xf)+1; + for(i = 0; i < nio; i++){ + ct->io[i].start = getlong(cis, (c>>4)&0x3); + ct->io[i].len = getlong(cis, (c>>6)&0x3)+1; + } + ct->nio = nio; +} + +static void +irq(Cisdat *cis, PCMconftab *ct) +{ + uchar c; + + if(readc(cis, &c) != 1) + return; + ct->irqtype = c & 0xe0; + if(c & 0x10) + ct->irqs = getlong(cis, 2); + else + ct->irqs = 1<<(c&0xf); + ct->irqs &= 0xDEB8; /* levels available to card */ +} + +static void +memspace(Cisdat *cis, int asize, int lsize, int host) +{ + ulong haddress, address, len; + + len = getlong(cis, lsize)*256; + address = getlong(cis, asize)*256; + USED(len, address); + if(host){ + haddress = getlong(cis, asize)*256; + USED(haddress); + } +} + +static void +tentry(PCMslot *pp, Cisdat *cis, int ) +{ + uchar c, i, feature; + PCMconftab *ct; + + if(pp->nctab >= nelem(pp->ctab)) + return; + if(readc(cis, &c) != 1) + return; + ct = &pp->ctab[pp->nctab++]; + + /* copy from last default config */ + if(pp->def) + *ct = *pp->def; + + ct->index = c & 0x3f; + + /* is this the new default? */ + if(c & 0x40) + pp->def = ct; + + /* memory wait specified? */ + if(c & 0x80){ + if(readc(cis, &i) != 1) + return; + if(i&0x80) + ct->memwait = 1; + } + + if(readc(cis, &feature) != 1) + return; + switch(feature&0x3){ + case 1: + ct->vpp1 = ct->vpp2 = power(cis); + break; + case 2: + power(cis); + ct->vpp1 = ct->vpp2 = power(cis); + break; + case 3: + power(cis); + ct->vpp1 = power(cis); + ct->vpp2 = power(cis); + break; + default: + break; + } + if(feature&0x4) + timing(cis, ct); + if(feature&0x8) + iospaces(cis, ct); + if(feature&0x10) + irq(cis, ct); + switch((feature>>5)&0x3){ + case 1: + memspace(cis, 0, 2, 0); + break; + case 2: + memspace(cis, 2, 2, 0); + break; + case 3: + if(readc(cis, &c) != 1) + return; + for(i = 0; i <= (c&0x7); i++) + memspace(cis, (c>>5)&0x3, (c>>3)&0x3, c&0x80); + break; + } + pp->configed++; +} + +static void +tvers1(PCMslot *pp, Cisdat *cis, int ) +{ + uchar c, major, minor, last; + int i; + + if(readc(cis, &major) != 1) + return; + if(readc(cis, &minor) != 1) + return; + last = 0; + for(i = 0; i < sizeof(pp->verstr)-1; i++){ + if(readc(cis, &c) != 1) + return; + if(c == 0) + c = ';'; + if(c == '\n') + c = ';'; + if(c == 0xff) + break; + if(c == ';' && last == ';') + continue; + pp->verstr[i] = c; + last = c; + } + pp->verstr[i] = 0; +} + +static void +tlonglnkmfc(PCMslot *pp, Cisdat *cis, int) +{ + int i, npos, opos; + uchar nfn, space, expect, type, this, link; + + readc(cis, &nfn); + for(i = 0; i < nfn; i++){ + readc(cis, &space); + npos = getlong(cis, 4); + opos = cis->cispos; + cis->cispos = npos; + expect = Linktarget; + + while(1){ + this = cis->cispos; + if(readc(cis, &type) != 1) + break; + if(type == 0xFF) + break; + if(readc(cis, &link) != 1) + break; + + if(expect && expect != type){ + print("tlonglnkmfc: expected %X found %X\n", + expect, type); + break; + } + expect = 0; + + switch(type){ + default: + break; + case 0x15: + tvers1(pp, cis, type); + break; + case 0x1A: + tcfig(pp, cis, type); + break; + case 0x1B: + tentry(pp, cis, type); + break; + } + + if(link == 0xFF) + break; + cis->cispos = this + (2+link); + } + cis->cispos = opos; + } +} diff --git a/os/boot/pc/clock.c b/os/boot/pc/clock.c index 6c5694cd..169abd11 100644 --- a/os/boot/pc/clock.c +++ b/os/boot/pc/clock.c @@ -115,10 +115,13 @@ static X86type x86amd[] = { 5, 1, 23, "AMD-K5", }, /* guesswork */ { 5, 2, 23, "AMD-K5", }, /* guesswork */ { 5, 3, 23, "AMD-K5", }, /* guesswork */ + { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */ + { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */ { 5, 6, 11, "AMD-K6", }, /* trial and error */ { 5, 7, 11, "AMD-K6", }, /* trial and error */ { 5, 8, 11, "AMD-K6-2", }, /* trial and error */ { 5, 9, 11, "AMD-K6-III", },/* trial and error */ + { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */ { 6, 1, 11, "AMD-Athlon", },/* trial and error */ { 6, 2, 11, "AMD-Athlon", },/* trial and error */ @@ -164,7 +167,8 @@ cpuidentify(void) int cpuidax, cpuiddx; cpuid(cpuidid, &cpuidax, &cpuiddx); - if(strncmp(cpuidid, "AuthenticAMD", 12) == 0) + if(strncmp(cpuidid, "AuthenticAMD", 12) == 0 || + strncmp(cpuidid, "Geode by NSC", 12) == 0) t = x86amd; else t = x86intel; diff --git a/os/boot/pc/dat.h b/os/boot/pc/dat.h index f6d02d56..7f9326ca 100644 --- a/os/boot/pc/dat.h +++ b/os/boot/pc/dat.h @@ -64,6 +64,7 @@ typedef struct { extern uchar broadcast[Eaddrlen]; typedef struct Ureg Ureg; +#pragma incomplete Ureg typedef struct Segdesc { ulong d0; @@ -112,6 +113,7 @@ typedef struct ISAConf { typedef struct Pcidev Pcidev; typedef struct PCMmap PCMmap; +typedef struct PCMslot PCMslot; #define BOOTLINE ((char*)CONFADDR) @@ -132,6 +134,7 @@ enum { /* type */ Tsd = 0x02, Tether = 0x03, Tcd = 0x04, + Tbios = 0x05, Tany = -1, }; diff --git a/os/boot/pc/devbios.c b/os/boot/pc/devbios.c new file mode 100644 index 00000000..d178fe81 --- /dev/null +++ b/os/boot/pc/devbios.c @@ -0,0 +1,428 @@ +/* + * boot driver for BIOS devices + */ +#include <u.h> +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" +#include "ureg.h" +#include "fs.h" + +typedef uvlong Devbytes, Devsects; + +typedef struct Biosdrive Biosdrive; /* 1 drive -> ndevs */ +typedef struct Biosdev Biosdev; + +enum { + Debug = 0, + Maxdevs = 4, + + CF = 1, + Flopid = 0, /* first floppy */ + Baseid = 0x80, /* first disk */ + + /* bios calls: int 13 disk services */ + Biosinit = 0, /* initialise disk & floppy ctlrs */ + Biosdrvsts, + Bioschsrdsects, + Biosdrvparam = 8, + Biosctlrinit, + Biosreset = 0xd, /* reset disk */ + Biosdrvrdy = 0x10, + Biosdrvtype = 0x15, + Biosckext = 0x41, + Biosrdsect, + Biosedrvparam = 0x48, + + /* disk types */ + Typenone = 0, + Typedisk = 3, +}; + +struct Biosdrive { + int ndevs; +}; +struct Biosdev { + Devbytes size; + Devbytes offset; + uchar id; /* drive number; e.g., 0x80 */ + char type; + ushort sectsz; +}; + +typedef struct Extread { + uchar size; + uchar unused1; + uchar nsects; + uchar unused2; + ulong addr; /* segment:offset */ + uvlong stsect; /* starting sector */ +} Extread; +typedef struct Edrvparam { + /* from edd 1.1 spec */ + ushort size; /* max. buffer size */ + ushort flags; + ulong physcyls; + ulong physheads; + ulong phystracksects; + uvlong physsects; + ushort sectsz; + void *dpte; /* ~0ull: invalid */ + + /* remainder from edd 3.0 spec */ + ushort key; /* 0xbedd if present */ + uchar dpilen; + uchar unused1; + ushort unused2; + char bustype[4]; /* "PCI" or "ISA" */ + char ifctype[8]; /* "ATA", "ATAPI", "SCSI", "USB", "1394", "FIBRE" */ + uvlong ifcpath; + uvlong devpath; + uchar unused3; + uchar dpicksum; +} Edrvparam; + +void realmode(int intr, Ureg *ureg); /* from trap.c */ + +int onlybios0; +int biosinited; + +static Biosdev bdev[Maxdevs]; +static Biosdrive bdrive; +static Ureg regs; + +static int dreset(uchar drive); +static Devbytes extgetsize(Biosdev *); +static Devsects getsize(uchar drive, char *type); +static int islba(uchar drive); + +static int +biosdiskcall(Ureg *rp, uchar op, ulong bx, ulong dx, ulong si) +{ + memset(rp, 0, sizeof *rp); + rp->ax = op << 8; + rp->bx = bx; + rp->dx = dx; /* often drive id */ + rp->si = si; + /* pass command in *rp, get results from there */ + realmode(0x13, rp); + if (rp->flags & CF) { +// print("biosdiskcall: int 13 op 0x%ux drive 0x%lux failed, " +// "ah error code 0x%ux\n", op, dx, (uchar)(rp->ax >> 8)); + return -1; + } + return 0; +} + +/* + * Find out what the bios knows about devices. + * our boot device could be usb; ghod only knows where it will appear. + */ +int +biosinit(void) +{ + int devid, lba, mask, lastbit; + Devbytes size; + char type; + Biosdev *bdp; + static int beenhere; + + mask = lastbit = 0; + if (beenhere) + return mask; + beenhere = 1; + /* 9pxeload can't use bios int 13 calls; they wedge the machine */ + if (pxe || getconf("*nobiosload") != nil || onlybios0 || !biosinited) + return mask; + for (devid = 0; devid < (1 << 8) && bdrive.ndevs < Maxdevs; devid++) { + lba = islba(devid); + if(!lba /* || devid != Baseid && dreset(devid) < 0 */ ) + continue; + type = Typedisk; /* HACK */ + if (getsize(devid, &type) == 0) { /* no device, end of range */ + devid &= ~0xf; + devid += 0x10; + devid--; + continue; + } + lastbit = 1 << bdrive.ndevs; + mask |= lastbit; + bdp = &bdev[bdrive.ndevs]; + bdp->id = devid; + bdp->type = type; + size = extgetsize(bdp); + bdp->size = size; + print("bios%d: drive 0x%ux: %llud bytes, type %d\n", + bdrive.ndevs, devid, size, type); + bdrive.ndevs++; + } + /* + * bioses seem to only be able to read from drive number 0x80 + * and certainly can't read from the highest drive number when we + * call them, even if there is only one. attempting to read from + * the last drive number yields a hung machine or a two-minute pause. + */ + if (bdrive.ndevs > 0) { + if (bdrive.ndevs == 1) { + print("biosinit: sorry, only one bios drive; " + "can't read last one\n"); + onlybios0 = 1; + } else + biosinited = 1; + bdrive.ndevs--; /* omit last drive number; it can't be read */ + mask &= ~lastbit; + } + return mask; +} + +void +biosinitdev(int i, char *name) +{ + if(i >= bdrive.ndevs) + panic("biosinitdev"); + sprint(name, "bios%d", i); +} + +void +biosprintdevs(int i) +{ + if(i >= bdrive.ndevs){ + print("got a print for %d, only got %d\n", i, bdrive.ndevs); + panic("biosprintdevs"); + } + print(" bios%d", i); +} + +int +biosboot(int dev, char *file, Boot *b) +{ + Fs *fs; + + if(strncmp(file, "dos!", 4) == 0) + file += 4; + if(strchr(file, '!') != nil || strcmp(file, "") == 0) { + print("syntax is bios0!file\n"); + return -1; + } + + fs = biosgetfspart(dev, "9fat", 1); + if(fs == nil) + return -1; + return fsboot(fs, file, b); +} + +/* read n bytes at sector offset into a from drive id */ +long +sectread(Biosdev *bdp, void *a, long n, Devsects offset) +{ + uchar *biosparam, *cp; + Extread *erp; + + if(n < 0 || n > bdp->sectsz) + return -1; + if(Debug) + memset((uchar *)BIOSXCHG, 'r', bdp->sectsz); /* preclean the buffer. */ + + biosdiskcall(®s, Biosdrvrdy, 0, bdp->id, 0); + + /* space for a BIG sector, just in case... */ + biosparam = (uchar *)BIOSXCHG + 2*1024; + + /* read into BIOSXCHG */ + erp = (Extread *)biosparam; + memset(erp, 0, sizeof *erp); + erp->size = sizeof *erp; + erp->nsects = 1; + erp->addr = PADDR(BIOSXCHG); + erp->stsect = offset; + if (biosdiskcall(®s, Biosrdsect, 0, bdp->id, PADDR(erp)) < 0) { + print("sectread: bios failed to read %ld @ sector %lld of 0x%ux\n", + n, offset, bdp->id); + return -1; + } + + /* copy into caller's buffer */ + memmove(a, (char *)BIOSXCHG, n); + if(Debug){ + cp = (uchar *)BIOSXCHG; + print("-%ux %ux %ux %ux--%16.16s-\n", + cp[0], cp[1], cp[2], cp[3], (char *)cp + 480); + } + return n; +} + +/* not tested yet. */ +static int +dreset(uchar drive) +{ +if (0) { +print("devbios: resetting disk controllers..."); + biosdiskcall(®s, Biosinit, 0, drive, 0); +print("\n"); +} + return regs.ax? -1: 0; /* ax!=0 on error */ +} + +static int +islba(uchar drive) +{ + if (biosdiskcall(®s, Biosckext, 0x55aa, drive, 0) < 0) + return 0; + if(regs.bx != 0xaa55){ + print("islba: buggy bios\n"); + return 0; + } + if (Debug) + print("islba: drive 0x%ux extensions version %d.%d cx 0x%lux\n", + drive, (uchar)(regs.ax >> 8), + (uchar)regs.ax, regs.cx); /* cx: 4=edd, 1=use dap */ + return regs.cx & 1; /* dap bit */ +} + +/* + * works so so... some floppies are 0x80+x when they shouldn't be, + * and report lba even if they cannot... + */ +static Devsects +getsize(uchar id, char *typep) +{ + int dtype; + + if (biosdiskcall(®s, Biosdrvtype, 0x55aa, id, 0) < 0) + return 0; + + dtype = (ushort)regs.ax >> 8; + if(dtype == Typenone){ + print("no such device 0x%ux of type %d\n", id, dtype); + return 0; + } + if(dtype != Typedisk){ + print("non-disk device 0x%ux of type %d\n", id, dtype); + return 0; + } + *typep = dtype; + return (ushort)regs.cx | regs.dx << 16; +} + +/* extended get size */ +static Devbytes +extgetsize(Biosdev *bdp) +{ + Edrvparam *edp; + + edp = (Edrvparam *)BIOSXCHG; + memset(edp, 0, sizeof *edp); + edp->size = sizeof *edp; + edp->dpilen = 36; + if (biosdiskcall(®s, Biosedrvparam, 0, bdp->id, PADDR(edp)) < 0) + return 0; + if(Debug) { + print("extgetsize: drive 0x%ux info flags 0x%ux", + bdp->id, edp->flags); + if (edp->key == 0xbedd) + print(" %s %s", edp->bustype, edp->ifctype); + print("\n"); + } + if (edp->sectsz <= 0) { + print("extgetsize: drive 0x%ux: non-positive sector size\n", + bdp->id); + edp->sectsz = 1; /* don't divide by zero */ + } + bdp->sectsz = edp->sectsz; + return edp->physsects * edp->sectsz; +} + +long +biosread(Fs *fs, void *a, long n) +{ + int want, got, part; + long totnr, stuck; + Devbytes offset; + Biosdev *bdp; + + if(fs->dev > bdrive.ndevs) + return -1; + if (n <= 0) + return n; + bdp = &bdev[fs->dev]; + offset = bdp->offset; + stuck = 0; + for (totnr = 0; totnr < n && stuck < 4; totnr += got) { + want = bdp->sectsz; + if (totnr + want > n) + want = n - totnr; + if(Debug) + print("bios%d, read: %ld @ off %lld, want: %d, id: 0x%ux\n", + fs->dev, n, offset, want, bdp->id); + part = offset % bdp->sectsz; + if (part != 0) { /* back up to start of sector */ + offset -= part; + totnr -= part; + if (totnr < 0) { + print("biosread: negative count %ld\n", totnr); + return -1; + } + } + if ((vlong)offset < 0) { + print("biosread: negative offset %lld\n", offset); + return -1; + } + got = sectread(bdp, (char *)a + totnr, want, offset/bdp->sectsz); + if(got <= 0){ +// print("biosread: failed to read %ld @ off %lld of 0x%ux, " +// "want %d got %d\n", +// n, offset, bdp->id, want, got); + return -1; + } + offset += got; + bdp->offset = offset; + if (got < bdp->sectsz) + stuck++; /* we'll have to re-read this sector */ + else + stuck = 0; + } + return totnr; +} + +vlong +biosseek(Fs *fs, vlong off) +{ + if (off < 0) { + print("biosseek(fs, %lld) is illegal\n", off); + return -1; + } + if(fs->dev > bdrive.ndevs) { + print("biosseek: fs->dev %d > bdrive.ndevs %d\n", + fs->dev, bdrive.ndevs); + return -1; + } + bdev[fs->dev].offset = off; /* do not know size... (yet) */ + return off; +} + +void * +biosgetfspart(int i, char *name, int chatty) +{ + static Fs fs; + + if(strcmp(name, "9fat") != 0){ + if(chatty) + print("unknown partition bios%d!%s (use bios%d!9fat)\n", + i, name, i); + return nil; + } + + fs.dev = i; + fs.diskread = biosread; + fs.diskseek = biosseek; + + if(dosinit(&fs) < 0){ + if(chatty) + print("bios%d!%s does not contain a FAT file system\n", + i, name); + return nil; + } + return &fs; +} diff --git a/os/boot/pc/devbios.h b/os/boot/pc/devbios.h new file mode 100644 index 00000000..08832996 --- /dev/null +++ b/os/boot/pc/devbios.h @@ -0,0 +1,22 @@ +typedef uvlong Devbytes, Devsects; + +typedef struct Biosdrive Biosdrive; /* 1 drive -> ndevs */ +typedef struct Biosdev Biosdev; + +struct Biosdrive { + int ndevs; +}; +struct Biosdev { + Devbytes size; + Devbytes offset; + uchar id; + char type; +}; + +int biosboot(int dev, char *file, Boot *b); +void* biosgetfspart(int i, char *name, int chatty); +void biosinitdev(int i, char *name); +int biosinit(void); +void biosprintbootdevs(int dev); +void biosprintdevs(int i); +long biosread(Fs *fs, void *a, long n); diff --git a/os/boot/pc/devi82365.c b/os/boot/pc/devi82365.c index a4e09d2d..456d911d 100644 --- a/os/boot/pc/devi82365.c +++ b/os/boot/pc/devi82365.c @@ -7,15 +7,7 @@ #include "io.h" /* - * Support for up to 4 Slot card slots. Generalizing above that is hard - * since addressing is not obvious. - presotto - * - * WARNING: This has never been tried with more than one card slot. - */ - -/* - * Intel 82365SL PCIC controller for the PCMCIA or - * Cirrus Logic PD6710/PD6720 which is mostly register compatible + * Intel 82365SL PCIC controller and compatibles. */ enum { @@ -84,10 +76,6 @@ enum Moffhi= 0x5, /* Card memory offset address high byte */ Fregactive= (1<<6), /* attribute memory */ - Mbits= 13, /* msb of Mchunk */ - Mchunk= 1<<Mbits, /* logical mapping granularity */ - Nmap= 4, /* max number of maps to use */ - /* * configuration registers - they start at an offset in attribute * memory found in the CIS. @@ -95,8 +83,12 @@ enum Rconfig= 0, Creset= (1<<7), /* reset device */ Clevel= (1<<6), /* level sensitive interrupt line */ - - Maxctab= 8, /* maximum configuration table entries */ + Cirq= (1<<2), /* IRQ enable */ + Cdecode= (1<<1), /* address decode */ + Cfunc= (1<<0), /* function enable */ + Riobase0= 5, + Riobase1= 6, + Riosize= 9, }; static int pcmcia_pcmspecial(char *, ISAConf *); @@ -105,9 +97,7 @@ static void pcmcia_pcmspecialclose(int); #define MAP(x,o) (Rmap + (x)*0x8 + o) typedef struct I82365 I82365; -typedef struct Slot Slot; -typedef struct Conftab Conftab; -typedef struct Cisdat Cisdat; + /* a controller */ enum { @@ -127,96 +117,29 @@ struct I82365 }; static I82365 *controller[4]; static int ncontroller; - -/* configuration table entry */ -struct Conftab -{ - int index; - ushort irqs; /* legal irqs */ - uchar irqtype; - uchar bit16; /* true for 16 bit access */ - struct { - ulong start; - ulong len; - } io[16]; - int nio; - uchar vpp1; - uchar vpp2; - uchar memwait; - ulong maxwait; - ulong readywait; - ulong otherwait; -}; - -/* cis memory walking */ -struct Cisdat -{ - uchar *cisbase; - int cispos; - int cisskip; - int cislen; -}; - -/* a card slot */ -struct Slot -{ - Lock; - int ref; - - I82365 *cp; /* controller for this slot */ - long memlen; /* memory length */ - uchar base; /* index register base */ - uchar slotno; /* slot number */ - - /* status */ - uchar special; /* in use for a special device */ - uchar already; /* already inited */ - uchar occupied; - uchar battery; - uchar wrprot; - uchar powered; - uchar configed; - uchar enabled; - uchar busy; - - /* cis info */ - char verstr[512]; /* version string */ - uchar cpresent; /* config registers present */ - ulong caddr; /* relative address of config registers */ - int nctab; /* number of config table entries */ - Conftab ctab[Maxctab]; - Conftab *def; /* default conftab */ - - /* for walking through cis */ - Cisdat; - - /* memory maps */ - Lock mlock; /* lock down the maps */ - int time; - PCMmap mmap[Nmap]; /* maps, last is always for the kernel */ -}; -static Slot *slot; -static Slot *lastslot; +static PCMslot *slot; +static PCMslot *lastslot; static nslot; -static void cisread(Slot*); static void i82365intr(Ureg*, void*); static void i82365reset(void); static int pcmio(int, ISAConf*); -static long pcmread(int, int, void*, long, vlong); -static long pcmwrite(int, int, void*, long, vlong); -static void i82365dump(Slot*); +static void i82365dump(PCMslot*); void devi82365link(void) { static int already; + char *p; if(already) return; already = 1; + if((p=getconf("pcmcia0")) && strncmp(p, "disabled", 8)==0) + return; + if (_pcmspecial) return; @@ -228,23 +151,23 @@ devi82365link(void) * reading and writing card registers */ static uchar -rdreg(Slot *pp, int index) +rdreg(PCMslot *pp, int index) { - outb(pp->cp->xreg, pp->base + index); - return inb(pp->cp->dreg); + outb(((I82365*)pp->cp)->xreg, pp->base + index); + return inb(((I82365*)pp->cp)->dreg); } static void -wrreg(Slot *pp, int index, uchar val) +wrreg(PCMslot *pp, int index, uchar val) { - outb(pp->cp->xreg, pp->base + index); - outb(pp->cp->dreg, val); + outb(((I82365*)pp->cp)->xreg, pp->base + index); + outb(((I82365*)pp->cp)->dreg, val); } /* * get info about card */ static void -slotinfo(Slot *pp) +slotinfo(PCMslot *pp) { uchar isr; @@ -254,6 +177,7 @@ slotinfo(Slot *pp) pp->battery = (isr & 3) == 3; pp->wrprot = isr & (1<<4); pp->busy = isr & (1<<5); + //pp->msec = TK2MS(MACHP(0)->ticks); } static int @@ -273,7 +197,7 @@ vcode(int volt) * enable the slot card */ static void -slotena(Slot *pp) +slotena(PCMslot *pp) { if(pp->enabled) return; @@ -289,7 +213,7 @@ slotena(Slot *pp) /* get configuration */ slotinfo(pp); if(pp->occupied){ - cisread(pp); + pcmcisread(pp); pp->enabled = 1; } else wrreg(pp, Rpc, Fautopower); @@ -299,7 +223,7 @@ slotena(Slot *pp) * disable the slot card */ static void -slotdis(Slot *pp) +slotdis(PCMslot *pp) { wrreg(pp, Rpc, 0); /* turn off card power */ wrreg(pp, Rwe, 0); /* no windows */ @@ -313,7 +237,7 @@ static void i82365intr(Ureg *, void *) { uchar csc, was; - Slot *pp; + PCMslot *pp; if(slot == 0) return; @@ -342,7 +266,7 @@ enum PCMmap* pcmmap(int slotno, ulong offset, int len, int attr) { - Slot *pp; + PCMslot *pp; uchar we, bit; PCMmap *m, *nm; int i; @@ -362,7 +286,7 @@ pcmmap(int slotno, ulong offset, int len, int attr) we = rdreg(pp, Rwe); bit = 1; nm = 0; - for(m = pp->mmap; m < &pp->mmap[Nmap]; m++){ + for(m = pp->mmap; m < &pp->mmap[nelem(pp->mmap)]; m++){ if((we & bit)) if(m->attr == attr) if(offset >= m->ca && e <= m->cea){ @@ -422,7 +346,7 @@ pcmmap(int slotno, ulong offset, int len, int attr) void pcmunmap(int slotno, PCMmap* m) { - Slot *pp; + PCMslot *pp; pp = slot + slotno; lock(&pp->mlock); @@ -431,7 +355,7 @@ pcmunmap(int slotno, PCMmap* m) } static void -increfp(Slot *pp) +increfp(PCMslot *pp) { lock(pp); if(pp->ref++ == 0) @@ -440,7 +364,7 @@ increfp(Slot *pp) } static void -decrefp(Slot *pp) +decrefp(PCMslot *pp) { lock(pp); if(pp->ref-- == 1) @@ -454,7 +378,7 @@ decrefp(Slot *pp) static int pcmcia_pcmspecial(char *idstr, ISAConf *isa) { - Slot *pp; + PCMslot *pp; extern char *strstr(char*, char*); int enabled; @@ -472,9 +396,11 @@ pcmcia_pcmspecial(char *idstr, ISAConf *isa) } if(pp->occupied) { - if(strstr(pp->verstr, idstr)) { - if (!enabled) + if(strstr(pp->verstr, idstr)){ + if (!enabled){ + enabled = 1; increfp(pp); + } if(isa == 0 || pcmio(pp->slotno, isa) == 0){ pp->special = 1; return pp->slotno; @@ -491,7 +417,7 @@ pcmcia_pcmspecial(char *idstr, ISAConf *isa) static void pcmcia_pcmspecialclose(int slotno) { - Slot *pp; + PCMslot *pp; print("pcmspecialclose called\n"); if(slotno >= nslot) @@ -520,7 +446,9 @@ i82365probe(int x, int d, int dev) outb(x, Rid + (dev<<7)); id = inb(d); if((id & 0xf0) != 0x80) - return 0; /* not this family */ + return 0; /* not a memory & I/O card */ + if((id & 0x0f) == 0x00) + return 0; /* no revision number, not possible */ cp = xalloc(sizeof(I82365)); cp->xreg = x; @@ -556,18 +484,22 @@ i82365probe(int x, int d, int dev) break; } + /* if it's not a Cirrus, it could be a Vadem... */ if(cp->type == Ti82365){ + /* unlock the Vadem extended regs */ outb(x, 0x0E + (dev<<7)); outb(x, 0x37 + (dev<<7)); + + /* make the id register show the Vadem id */ outb(x, 0x3A + (dev<<7)); c = inb(d); outb(d, c|0xC0); outb(x, Rid + (dev<<7)); c = inb(d); - if(c != id && !(c & 0x08)) - print("#y%d: id %uX changed to %uX\n", ncontroller, id, c); if(c & 0x08) cp->type = Tvg46x; + + /* go back to Intel compatible id */ outb(x, 0x3A + (dev<<7)); c = inb(d); outb(d, c & ~0xC0); @@ -592,7 +524,7 @@ i82365probe(int x, int d, int dev) } static void -i82365dump(Slot *pp) +i82365dump(PCMslot *pp) { int i; @@ -615,7 +547,7 @@ i82365reset(void) static int already; int i, j; I82365 *cp; - Slot *pp; + PCMslot *pp; if(already) return; @@ -630,9 +562,8 @@ i82365reset(void) for(i = 0; i < ncontroller; i++) nslot += controller[i]->nslot; - slot = xalloc(nslot * sizeof(Slot)); + slot = xalloc(nslot * sizeof(PCMslot)); - /* if the card is there turn on 5V power to keep its battery alive */ lastslot = slot; for(i = 0; i < ncontroller; i++){ cp = controller[i]; @@ -644,6 +575,8 @@ i82365reset(void) pp->memlen = 64*MB; pp->base = (cp->dev<<7) | (j<<6); pp->cp = cp; + pp->msec = ~0; + pp->verstr[0] = 0; slotdis(pp); /* interrupt on status change */ @@ -657,15 +590,15 @@ i82365reset(void) } /* - * configure the Slot for IO. We assume very heavily that we can read + * configure the PCMslot for IO. We assume very heavily that we can read * configuration info from the CIS. If not, we won't set up correctly. */ static int pcmio(int slotno, ISAConf *isa) { uchar we, x, *p; - Slot *pp; - Conftab *ct, *et, *t; + PCMslot *pp; + PCMconftab *ct, *et, *t; PCMmap *m; int i, index, irq; char *cp; @@ -692,6 +625,7 @@ pcmio(int slotno, ISAConf *isa) return -1; ct = &pp->ctab[index]; } + if(ct == 0){ /* assume default is right */ @@ -749,7 +683,10 @@ pcmio(int slotno, ISAConf *isa) x |= x<<4; wrreg(pp, Rio, x); - /* enable io port map 0 */ + /* + * enable io port map 0 + * the 'top' register value includes the last valid address + */ if(isa->port == 0) isa->port = ct->io[0].start; we = rdreg(pp, Rwe); @@ -759,7 +696,7 @@ pcmio(int slotno, ISAConf *isa) wrreg(pp, Riotop0lo, i); wrreg(pp, Riotop0hi, i>>8); we |= 1<<6; - if(ct->nio == 2 && ct->io[1].start){ + if(ct->nio >= 2 && ct->io[1].start){ wrreg(pp, Riobtm1lo, ct->io[1].start); wrreg(pp, Riobtm1hi, ct->io[1].start>>8); i = ct->io[1].start+ct->io[1].len-1; @@ -770,436 +707,36 @@ pcmio(int slotno, ISAConf *isa) wrreg(pp, Rwe, we); /* only touch Rconfig if it is present */ - if(pp->cpresent & (1<<Rconfig)){ + m = pcmmap(slotno, pp->cfg[0].caddr + Rconfig, 0x20, 1); + p = KADDR(m->isa + pp->cfg[0].caddr - m->ca); + if(pp->cfg[0].cpresent & (1<<Rconfig)){ /* Reset adapter */ - m = pcmmap(slotno, pp->caddr + Rconfig, 1, 1); - p = KADDR(m->isa + pp->caddr + Rconfig - m->ca); - /* set configuration and interrupt type */ + /* set configuration and interrupt type. + * if level is possible on the card, use it. + */ x = ct->index; - if((ct->irqtype & 0x20) && ((ct->irqtype & 0x40)==0 || isa->irq>7)) + if(ct->irqtype & 0x20) x |= Clevel; - *p = x; - delay(5); - - pcmunmap(slotno, m); - } - return 0; -} - -/* - * read and crack the card information structure enough to set - * important parameters like power - */ -static void tcfig(Slot*, Cisdat*, int); -static void tentry(Slot*, Cisdat*, int); -static void tvers1(Slot*, Cisdat*, int); - -struct { - int n; - void (*parse)(Slot*, Cisdat*, int); -} cistab[] = { - 0x15, tvers1, - 0x1A, tcfig, - 0x1B, tentry, -}; - -static int -readc(Cisdat *pp, uchar *x) -{ - if(pp->cispos >= pp->cislen) - return 0; - *x = pp->cisbase[pp->cisskip*pp->cispos]; - pp->cispos++; - return 1; -} - -static int -xcistuple(int slotno, int tuple, void *v, int nv, int attr) -{ - PCMmap *m; - Cisdat cis; - int i, l; - uchar *p; - uchar type, link; - int this; - - m = pcmmap(slotno, 0, 0, attr); - if(m == 0) { -if(debug) print("could not map\n"); - return -1; - } - - cis.cisbase = KADDR(m->isa); - cis.cispos = 0; - cis.cisskip = attr ? 2 : 1; - cis.cislen = Mchunk; - -if(debug) print("cis %d %d #%lux srch %x...", attr, cis.cisskip, cis.cisbase, tuple); - /* loop through all the tuples */ - for(i = 0; i < 1000; i++){ - this = cis.cispos; - if(readc(&cis, &type) != 1) - break; -if(debug) print("%2ux...", type); - if(type == 0xFF) - break; - if(readc(&cis, &link) != 1) - break; - if(link == 0xFF) - break; - if(type == tuple) { - p = v; - for(l=0; l<nv && l<link; l++) - if(readc(&cis, p++) != 1) - break; - pcmunmap(slotno, m); -if(debug) print("pcm find %2.2ux %d %d\n", type, link, l); - return l; - } - cis.cispos = this + (2+link); - } - pcmunmap(slotno, m); - return -1; -} - -int -pcmcistuple(int slotno, int tuple, void *v, int nv) -{ - int n; - - /* try attribute space, then memory */ - if((n = xcistuple(slotno, tuple, v, nv, 1)) >= 0) - return n; - return xcistuple(slotno, tuple, v, nv, 0); -} - -static void -cisread(Slot *pp) -{ - uchar v[256]; - int i, nv; - Cisdat cis; - - memset(pp->ctab, 0, sizeof(pp->ctab)); - pp->caddr = 0; - pp->cpresent = 0; - pp->configed = 0; - pp->nctab = 0; - - for(i = 0; i < nelem(cistab); i++) { - if((nv = pcmcistuple(pp->slotno, cistab[i].n, v, sizeof(v))) >= 0) { - cis.cisbase = v; - cis.cispos = 0; - cis.cisskip = 1; - cis.cislen = nv; - - (*cistab[i].parse)(pp, &cis, cistab[i].n); - } - } -} - -static ulong -getlong(Cisdat *cis, int size) -{ - uchar c; - int i; - ulong x; - - x = 0; - for(i = 0; i < size; i++){ - if(readc(cis, &c) != 1) - break; - x |= c<<(i*8); - } - return x; -} - -static void -tcfig(Slot *pp, Cisdat *cis, int ) -{ - uchar size, rasize, rmsize; - uchar last; - - if(readc(cis, &size) != 1) - return; - rasize = (size&0x3) + 1; - rmsize = ((size>>2)&0xf) + 1; - if(readc(cis, &last) != 1) - return; - pp->caddr = getlong(cis, rasize); - pp->cpresent = getlong(cis, rmsize); -} - -static ulong vexp[8] = -{ - 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 -}; -static ulong vmant[16] = -{ - 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90, -}; - -static ulong -microvolt(Cisdat *cis) -{ - uchar c; - ulong microvolts; - ulong exp; - - if(readc(cis, &c) != 1) - return 0; - exp = vexp[c&0x7]; - microvolts = vmant[(c>>3)&0xf]*exp; - while(c & 0x80){ - if(readc(cis, &c) != 1) - return 0; - switch(c){ - case 0x7d: - break; /* high impedence when sleeping */ - case 0x7e: - case 0x7f: - microvolts = 0; /* no connection */ - break; - default: - exp /= 10; - microvolts += exp*(c&0x7f); - } - } - return microvolts; -} - -static ulong -nanoamps(Cisdat *cis) -{ - uchar c; - ulong nanoamps; - - if(readc(cis, &c) != 1) - return 0; - nanoamps = vexp[c&0x7]*vmant[(c>>3)&0xf]; - while(c & 0x80){ - if(readc(cis, &c) != 1) - return 0; - if(c == 0x7d || c == 0x7e || c == 0x7f) - nanoamps = 0; - } - return nanoamps; -} - -/* - * only nominal voltage is important for config - */ -static ulong -power(Cisdat *cis) -{ - uchar feature; - ulong mv; - - mv = 0; - if(readc(cis, &feature) != 1) - return 0; - if(feature & 1) - mv = microvolt(cis); - if(feature & 2) - microvolt(cis); - if(feature & 4) - microvolt(cis); - if(feature & 8) - nanoamps(cis); - if(feature & 0x10) - nanoamps(cis); - if(feature & 0x20) - nanoamps(cis); - if(feature & 0x40) - nanoamps(cis); - return mv/1000000; -} - -static ulong mantissa[16] = -{ 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, }; - -static ulong exponent[8] = -{ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, }; -static ulong -ttiming(Cisdat *cis, int scale) -{ - uchar unscaled; - ulong nanosecs; - - if(readc(cis, &unscaled) != 1) - return 0; - nanosecs = (mantissa[(unscaled>>3)&0xf]*exponent[unscaled&7])/10; - nanosecs = nanosecs * vexp[scale]; - return nanosecs; -} - -static void -timing(Cisdat *cis, Conftab *ct) -{ - uchar c, i; - - if(readc(cis, &c) != 1) - return; - i = c&0x3; - if(i != 3) - ct->maxwait = ttiming(cis, i); /* max wait */ - i = (c>>2)&0x7; - if(i != 7) - ct->readywait = ttiming(cis, i); /* max ready/busy wait */ - i = (c>>5)&0x7; - if(i != 7) - ct->otherwait = ttiming(cis, i); /* reserved wait */ -} - -static void -iospaces(Cisdat *cis, Conftab *ct) -{ - uchar c; - int i, nio; - - ct->nio = 0; - if(readc(cis, &c) != 1) - return; - - ct->bit16 = ((c>>5)&3) >= 2; - if(!(c & 0x80)){ - ct->io[0].start = 0; - ct->io[0].len = 1<<(c&0x1f); - ct->nio = 1; - return; - } - - if(readc(cis, &c) != 1) - return; - - nio = (c&0xf)+1; - for(i = 0; i < nio; i++){ - ct->io[i].start = getlong(cis, (c>>4)&0x3); - ct->io[i].len = getlong(cis, (c>>6)&0x3)+1; - } - ct->nio = nio; -} - -static void -irq(Cisdat *cis, Conftab *ct) -{ - uchar c; - - if(readc(cis, &c) != 1) - return; - ct->irqtype = c & 0xe0; - if(c & 0x10) - ct->irqs = getlong(cis, 2); - else - ct->irqs = 1<<(c&0xf); - ct->irqs &= 0xDEB8; /* levels available to card */ -} - -static void -memspace(Cisdat *cis, int asize, int lsize, int host) -{ - ulong haddress, address, len; - - len = getlong(cis, lsize)*256; - address = getlong(cis, asize)*256; - USED(len, address); - if(host){ - haddress = getlong(cis, asize)*256; - USED(haddress); - } -} - -static void -tentry(Slot *pp, Cisdat *cis, int ) -{ - uchar c, i, feature; - Conftab *ct; - - if(pp->nctab >= Maxctab) - return; - if(readc(cis, &c) != 1) - return; - ct = &pp->ctab[pp->nctab++]; - - /* copy from last default config */ - if(pp->def) - *ct = *pp->def; - - ct->index = c & 0x3f; - - /* is this the new default? */ - if(c & 0x40) - pp->def = ct; + /* enable the device, enable address decode and + * irq enable. + */ + x |= Cfunc|Cdecode|Cirq; - /* memory wait specified? */ - if(c & 0x80){ - if(readc(cis, &i) != 1) - return; - if(i&0x80) - ct->memwait = 1; + p[0] = x; + //delay(5); + microdelay(40); } - if(readc(cis, &feature) != 1) - return; - switch(feature&0x3){ - case 1: - ct->vpp1 = ct->vpp2 = power(cis); - break; - case 2: - power(cis); - ct->vpp1 = ct->vpp2 = power(cis); - break; - case 3: - power(cis); - ct->vpp1 = power(cis); - ct->vpp2 = power(cis); - break; - default: - break; - } - if(feature&0x4) - timing(cis, ct); - if(feature&0x8) - iospaces(cis, ct); - if(feature&0x10) - irq(cis, ct); - switch((feature>>5)&0x3){ - case 1: - memspace(cis, 0, 2, 0); - break; - case 2: - memspace(cis, 2, 2, 0); - break; - case 3: - if(readc(cis, &c) != 1) - return; - for(i = 0; i <= (c&0x7); i++) - memspace(cis, (c>>5)&0x3, (c>>3)&0x3, c&0x80); - break; + if(pp->cfg[0].cpresent & (1<<Riobase0)){ + /* set up the iobase 0 */ + p[Riobase0 << 1] = isa->port; + p[Riobase1 << 1] = isa->port >> 8; } - pp->configed++; -} -static void -tvers1(Slot *pp, Cisdat *cis, int ) -{ - uchar c, major, minor; - int i; - - if(readc(cis, &major) != 1) - return; - if(readc(cis, &minor) != 1) - return; - for(i = 0; i < sizeof(pp->verstr)-1; i++){ - if(readc(cis, &c) != 1) - return; - if(c == 0) - c = '\n'; - if(c == 0xff) - break; - pp->verstr[i] = c; - } - pp->verstr[i] = 0; + if(pp->cfg[0].cpresent & (1<<Riosize)) + p[Riosize << 1] = ct->io[0].len; + pcmunmap(slotno, m); + return 0; } diff --git a/os/boot/pc/devpccard.c b/os/boot/pc/devpccard.c index d5c96aa9..8db7545e 100644 --- a/os/boot/pc/devpccard.c +++ b/os/boot/pc/devpccard.c @@ -9,10 +9,7 @@ #include "error.h" #include "io.h" -#define ioalloc(addr, len, align, name) (addr) -#define iofree(addr) extern int pciscan(int, Pcidev **); -extern ulong pcibarsize(Pcidev *, int); int (*_pcmspecial)(char *, ISAConf *); void (*_pcmspecialclose)(int); @@ -33,7 +30,7 @@ pcmspecialclose(int a) static ulong ioreserve(ulong, int size, int align, char *) { - static ulong isaend = 0xfd00; + static ulong isaend = 0x400; /*0xfd00*/ ulong ioaddr; if (align) @@ -51,11 +48,16 @@ enum { TI_1250_did = 0xAC16, TI_1450_did = 0xAC1B, TI_1251A_did = 0xAC1D, + TI_1420_did = 0xAC51, Ricoh_vid = 0x1180, + Ricoh_475_did = 0x0475, Ricoh_476_did = 0x0476, Ricoh_478_did = 0x0478, + O2_vid = 0x1217, + O2_OZ711M3_did = 0x7134, + Nslots = 4, /* Maximum number of CardBus slots to use */ K = 1024, @@ -78,19 +80,23 @@ enum { TI1131xDC = 0x92, // device control }; -typedef struct { - ushort r_vid; - ushort r_did; - char *r_name; -} variant_t; +typedef struct Variant Variant; +struct Variant { + ushort vid; + ushort did; + char *name; +}; -static variant_t variant[] = { +static Variant variant[] = { +{ Ricoh_vid, Ricoh_475_did, "Ricoh 475 PCI/Cardbus bridge", }, { Ricoh_vid, Ricoh_476_did, "Ricoh 476 PCI/Cardbus bridge", }, { Ricoh_vid, Ricoh_478_did, "Ricoh 478 PCI/Cardbus bridge", }, -{ TI_vid, TI_1131_did, "TI PCI-1131 Cardbus Controller", }, -{ TI_vid, TI_1250_did, "TI PCI-1250 Cardbus Controller", }, -{ TI_vid, TI_1450_did, "TI PCI-1450 Cardbus Controller", }, -{ TI_vid, TI_1251A_did, "TI PCI-1251A Cardbus Controller", }, +{ TI_vid, TI_1131_did, "TI PCI-1131 Cardbus Controller", }, +{ TI_vid, TI_1250_did, "TI PCI-1250 Cardbus Controller", }, +{ TI_vid, TI_1450_did, "TI PCI-1450 Cardbus Controller", }, +{ TI_vid, TI_1251A_did, "TI PCI-1251A Cardbus Controller", }, +{ TI_vid, TI_1420_did, "TI PCI-1420 Cardbus Controller", }, +{ O2_vid, O2_OZ711M3_did, "O2Micro OZ711M3 MemoryCardBus", }, }; /* Cardbus registers */ @@ -119,6 +125,8 @@ enum { PciPCR_MEM = 1 << 1, PciPCR_Master = 1 << 2, + PciPMC = 0xa4, + Nbars = 6, Ncmd = 10, CBIRQ = 9, @@ -134,13 +142,6 @@ enum { Tvg46x, }; -static char *chipname[] = { -[Ti82365] "Intel 82365SL", -[Tpd6710] "Cirrus Logic PD6710", -[Tpd6720] "Cirrus Logic PD6720", -[Tvg46x] "Vadem VG-46x", -}; - /* * Intel 82365SL PCIC controller for the PCMCIA or * Cirrus Logic PD6710/PD6720 which is mostly register compatible @@ -226,70 +227,48 @@ enum * important parameters like power */ /* cis memory walking */ -typedef struct Cisdat { +typedef struct Cisdat Cisdat; +struct Cisdat { uchar *cisbase; - int cispos; - int cisskip; - int cislen; -} Cisdat; - -/* configuration table entry */ -typedef struct PCMconftab PCMconftab; -struct PCMconftab -{ - int index; - ushort irqs; /* legal irqs */ - uchar irqtype; - uchar bit16; /* true for 16 bit access */ - struct { - ulong start; - ulong len; - } io[16]; - int nio; - uchar vpp1; - uchar vpp2; - uchar memwait; - ulong maxwait; - ulong readywait; - ulong otherwait; + int cispos; + int cisskip; + int cislen; }; -typedef struct { - char pi_verstr[512]; /* Version string */ - PCMmap pi_mmap[4]; /* maps, last is always for the kernel */ - ulong pi_conf_addr; /* Config address */ - uchar pi_conf_present; /* Config register present */ - int pi_nctab; /* In use configuration tables */ - PCMconftab pi_ctab[8]; /* Configuration tables */ - PCMconftab *pi_defctab; /* Default conftab */ - - int pi_port; /* Actual port usage */ - int pi_irq; /* Actual IRQ usage */ -} pcminfo_t; - -#define qlock(i) {/* nothing to do */;} -#define qunlock(i) {/* nothing to do */;} -typedef struct QLock { int r; } QLock; - -typedef struct { - QLock; - variant_t *cb_variant; /* Which CardBus chipset */ - Pcidev *cb_pci; /* The bridge itself */ - ulong *cb_regs; /* Cardbus registers */ - int cb_ltype; /* Legacy type */ - int cb_lindex; /* Legacy port index address */ - int cb_ldata; /* Legacy port data address */ - int cb_lbase; /* Base register for this socket */ - - int cb_state; /* Current state of card */ - int cb_type; /* Type of card */ - pcminfo_t cb_linfo; /* PCMCIA slot info */ - - int cb_refs; /* Number of refs to slot */ - QLock cb_refslock; /* inc/dev ref lock */ -} cb_t; - -static int managerstarted; +typedef struct Pcminfo Pcminfo; +struct Pcminfo { + char verstr[512]; /* Version string */ + PCMmap mmap[4]; /* maps, last is always for the kernel */ + ulong conf_addr; /* Config address */ + uchar conf_present; /* Config register present */ + int nctab; /* In use configuration tables */ + PCMconftab ctab[8]; /* Configuration tables */ + PCMconftab *defctab; /* Default conftab */ + + int port; /* Actual port usage */ + int irq; /* Actual IRQ usage */ +}; + +typedef struct Cardbus Cardbus; +struct Cardbus { + Lock; + Variant *variant; /* Which CardBus chipset */ + Pcidev *pci; /* The bridge itself */ + ulong *regs; /* Cardbus registers */ + int ltype; /* Legacy type */ + int lindex; /* Legacy port index address */ + int ldata; /* Legacy port data address */ + int lbase; /* Base register for this socket */ + + int state; /* Current state of card */ + int type; /* Type of card */ + Pcminfo linfo; /* PCMCIA slot info */ + + int special; /* card is allocated to a driver */ + + int refs; /* Number of refs to slot */ + Lock refslock; /* inc/dev ref lock */ +}; enum { Mshift= 12, @@ -297,7 +276,7 @@ enum { Mmask= ~(Mgran-1), /* mask for address bits important to the chip */ }; -static cb_t cbslots[Nslots]; +static Cardbus cbslots[Nslots]; static int nslots; static ulong exponent[8] = { @@ -312,28 +291,26 @@ static ulong mantissa[16] = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, }; -static char Enocard[] = "No card in slot"; - static void cbint(Ureg *, void *); -static int powerup(cb_t *); -static void configure(cb_t *); -static void managecard(cb_t *); +static int powerup(Cardbus *); +static void configure(Cardbus *); +static void managecard(Cardbus *); static void cardmanager(void *); -static void eject(cb_t *); +static void eject(Cardbus *); static void interrupt(Ureg *, void *); -static void powerdown(cb_t *cb); -static void unconfigure(cb_t *cb); +static void powerdown(Cardbus *cb); +static void unconfigure(Cardbus *cb); -static void i82365probe(cb_t *cb, int lindex, int ldata); -static void i82365configure(cb_t *cb); -static PCMmap *isamap(cb_t *cb, ulong offset, int len, int attr); +static void i82365probe(Cardbus *cb, int lindex, int ldata); +static void i82365configure(Cardbus *cb); +static PCMmap *isamap(Cardbus *cb, ulong offset, int len, int attr); static void isaunmap(PCMmap* m); -static uchar rdreg(cb_t *cb, int index); -static void wrreg(cb_t *cb, int index, uchar val); +static uchar rdreg(Cardbus *cb, int index); +static void wrreg(Cardbus *cb, int index, uchar val); static int readc(Cisdat *cis, uchar *x); -static void tvers1(cb_t *cb, Cisdat *cis, int ); -static void tcfig(cb_t *cb, Cisdat *cis, int ); -static void tentry(cb_t *cb, Cisdat *cis, int ); +static void tvers1(Cardbus *cb, Cisdat *cis, int ); +static void tcfig(Cardbus *cb, Cisdat *cis, int ); +static void tentry(Cardbus *cb, Cisdat *cis, int ); static int vcode(int volt); static int pccard_pcmspecial(char *idstr, ISAConf *isa); static void pccard_pcmspecialclose(int slotno); @@ -361,29 +338,29 @@ enum { static char *states[] = { [SlotEmpty] "SlotEmpty", -[SlotFull] "SlotFull", +[SlotFull] "SlotFull", [SlotPowered] "SlotPowered", [SlotConfigured] "SlotConfigured", }; static void -engine(cb_t *cb, int message) +engine(Cardbus *cb, int message) { // print("engine(%d): %s(%s)\n", - // (int)(cb - cbslots), states[cb->cb_state], messages[message]); - switch (cb->cb_state) { + // (int)(cb - cbslots), states[cb->state], messages[message]); + switch (cb->state) { case SlotEmpty: switch (message) { case CardDetected: - cb->cb_state = SlotFull; + cb->state = SlotFull; powerup(cb); break; case CardEjected: break; default: - print("#Y%d: Invalid message %s in SlotEmpty state\n", - (int)(cb - cbslots), messages[message]); + //print("#Y%d: Invalid message %s in SlotEmpty state\n", + // (int)(cb - cbslots), messages[message]); break; } break; @@ -392,11 +369,11 @@ engine(cb_t *cb, int message) switch (message) { case CardPowered: - cb->cb_state = SlotPowered; + cb->state = SlotPowered; configure(cb); break; case CardEjected: - cb->cb_state = SlotEmpty; + cb->state = SlotEmpty; powerdown(cb); break; default: @@ -410,10 +387,10 @@ engine(cb_t *cb, int message) switch (message) { case CardConfigured: - cb->cb_state = SlotConfigured; + cb->state = SlotConfigured; break; case CardEjected: - cb->cb_state = SlotEmpty; + cb->state = SlotEmpty; unconfigure(cb); powerdown(cb); break; @@ -428,141 +405,36 @@ engine(cb_t *cb, int message) switch (message) { case CardEjected: - cb->cb_state = SlotEmpty; + cb->state = SlotEmpty; unconfigure(cb); powerdown(cb); break; default: - print("#Y%d: Invalid message %s in SlotConfigured state\n", - (int)(cb - cbslots), messages[message]); + //print("#Y%d: Invalid message %s in SlotConfigured state\n", + // (int)(cb - cbslots), messages[message]); break; } break; } } -static void -qengine(cb_t *cb, int message) -{ - qlock(cb); - engine(cb, message); - qunlock(cb); -} - -typedef struct { - cb_t *e_cb; - int e_message; -} events_t; - -static Lock levents; -static events_t events[NUMEVENTS]; -// static Rendez revents; -static int nevents; - -//static void -//iengine(cb_t *cb, int message) -//{ -// if (nevents >= NUMEVENTS) { -// print("#Y: Too many events queued, discarding request\n"); -// return; -// } -// ilock(&levents); -// events[nevents].e_cb = cb; -// events[nevents].e_message = message; -// nevents++; -// iunlock(&levents); -// wakeup(&revents); -//} - -static int -eventoccured(void) -{ - return nevents > 0; -} - -// static void -// processevents(void *) -// { -// while (1) { -// int message; -// cb_t *cb; -// -// sleep(&revents, (int (*)(void *))eventoccured, nil); -// -// cb = nil; -// message = 0; -// ilock(&levents); -// if (nevents > 0) { -// cb = events[0].e_cb; -// message = events[0].e_message; -// nevents--; -// if (nevents > 0) -// memmove(events, &events[1], nevents * sizeof(events_t)); -// } -// iunlock(&levents); -// -// if (cb) -// qengine(cb, message); -// } -// } - -// static void -// interrupt(Ureg *, void *) -// { -// int i; -// -// for (i = 0; i != nslots; i++) { -// cb_t *cb = &cbslots[i]; -// ulong event, state; -// -// event= cb->cb_regs[SocketEvent]; -// state = cb->cb_regs[SocketState]; -// rdreg(cb, Rcsc); /* Ack the interrupt */ -// -// print("interrupt: slot %d, event %.8lX, state %.8lX, (%s)\n", -// (int)(cb - cbslots), event, state, states[cb->cb_state]); -// -// if (event & SE_CCD) { -// cb->cb_regs[SocketEvent] |= SE_CCD; /* Ack interrupt */ -// if (state & SE_CCD) { -// if (cb->cb_state != SlotEmpty) { -// print("#Y: take cardejected interrupt\n"); -// iengine(cb, CardEjected); -// } -// } -// else -// iengine(cb, CardDetected); -// } -// -// if (event & SE_POWER) { -// cb->cb_regs[SocketEvent] |= SE_POWER; /* Ack interrupt */ -// iengine(cb, CardPowered); -// } -// } -// } - void devpccardlink(void) { static int initialized; Pcidev *pci; int i; -// uchar intl; + char *p; if (initialized) return; initialized = 1; - if (!getconf("pccard0")) + if((p=getconf("pccard0")) && strncmp(p, "disabled", 8)==0) return; - if (_pcmspecial) { - print("#Y: CardBus and PCMCIA at the same time?\n"); + if(_pcmspecial) return; - } - - _pcmspecial = pccard_pcmspecial; - _pcmspecialclose = pccard_pcmspecialclose; /* Allocate legacy space */ @@ -571,15 +443,16 @@ devpccardlink(void) /* Find all CardBus controllers */ pci = nil; -// intl = (uchar)-1; while ((pci = pcimatch(pci, 0, 0)) != nil) { ulong baddr; uchar pin; - cb_t *cb; + Cardbus *cb; int slot; + if(pci->ccrb != 6 || pci->ccru != 7) + continue; for (i = 0; i != nelem(variant); i++) - if (pci->vid == variant[i].r_vid && pci->did == variant[i].r_did) + if (pci->vid == variant[i].vid && pci->did == variant[i].did) break; if (i == nelem(variant)) continue; @@ -588,8 +461,27 @@ devpccardlink(void) slot = nslots++; cb = &cbslots[slot]; - cb->cb_pci = pci; - cb->cb_variant = &variant[i]; + cb->pci = pci; + cb->variant = &variant[i]; + + // Set up PCI bus numbers if needed. + if (pcicfgr8(pci, PciSBN) == 0) { + static int busbase = 0x20; + + pcicfgw8(pci, PciSBN, busbase); + pcicfgw8(pci, PciUBN, busbase + 2); + busbase += 3; + } + + // Patch up intl if needed. + if ((pin = pcicfgr8(pci, PciINTP)) != 0 && + (pci->intl == 0xff || pci->intl == 0)) { + pci->intl = pciipin(nil, pin); + pcicfgw8(pci, PciINTL, pci->intl); + + if (pci->intl == 0xff || pci->intl == 0) + print("#Y%d: No interrupt?\n", (int)(cb - cbslots)); + } // Don't you love standards! if (pci->vid == TI_vid) { @@ -616,84 +508,73 @@ devpccardlink(void) else if (pci->did == TI_1250_did) { print("No support yet for the TI_1250_did, prod pb\n"); } - } - -// if (intl != -1 && intl != pci->intl) -// intrenable(pci->intl, interrupt, cb, pci->tbdf, "cardbus"); -// intl = pci->intl; - - // Set up PCI bus numbers if needed. - if (pcicfgr8(pci, PciSBN) == 0) { - static int busbase = 0x20; - - pcicfgw8(pci, PciSBN, busbase); - pcicfgw8(pci, PciUBN, busbase + 2); - busbase += 3; - } - - // Patch up intl if needed. - if ((pin = pcicfgr8(pci, PciINTP)) != 0 && - (pci->intl == 0xff || pci->intl == 0)) { - pci->intl = pciipin(nil, pin); - pcicfgw8(pci, PciINTL, pci->intl); - - if (pci->intl == 0xff || pci->intl == 0) - print("#Y%d: No interrupt?\n", (int)(cb - cbslots)); + else if (pci->did == TI_1420_did) { + // Disable Vcc protection + pcicfgw32(cb->pci, 0x80, + pcicfgr32(cb->pci, 0x80) | (1 << 21)); + } + + pcicfgw16(cb->pci, PciPMC, pcicfgr16(cb->pci, PciPMC) & ~3); } - if ((baddr = pcicfgr32(cb->cb_pci, PciBAR0)) == 0) { - int align = (pci->did == Ricoh_478_did)? 0x10000: 0x1000; + if ((baddr = pcicfgr32(cb->pci, PciBAR0)) == 0) { + int size = (pci->did == Ricoh_478_did)? 0x10000: 0x1000; - baddr = upamalloc(baddr, align, align); - pcicfgw32(cb->cb_pci, PciBAR0, baddr); - cb->cb_regs = (ulong *)KADDR(baddr); + baddr = upamalloc(baddr, size, size); + pcicfgw32(cb->pci, PciBAR0, baddr); + cb->regs = (ulong *)KADDR(baddr); } else - cb->cb_regs = (ulong *)KADDR(upamalloc(baddr, 4096, 0)); - cb->cb_state = SlotEmpty; + cb->regs = (ulong *)KADDR(upamalloc(baddr, 4096, 0)); + cb->state = SlotEmpty; /* Don't really know what to do with this... */ i82365probe(cb, LegacyAddr, LegacyAddr + 1); print("#Y%ld: %s, %.8ulX intl %d\n", cb - cbslots, - variant[i].r_name, baddr, pci->intl); + variant[i].name, baddr, pci->intl); } if (nslots == 0) return; + _pcmspecial = pccard_pcmspecial; + _pcmspecialclose = pccard_pcmspecialclose; + for (i = 0; i != nslots; i++) { - cb_t *cb = &cbslots[i]; + Cardbus *cb = &cbslots[i]; - if ((cb->cb_regs[SocketState] & SE_CCD) == 0) + if ((cb->regs[SocketState] & SE_CCD) == 0) engine(cb, CardDetected); } delay(500); /* Allow time for power up */ for (i = 0; i != nslots; i++) { - cb_t *cb = &cbslots[i]; + Cardbus *cb = &cbslots[i]; - if (cb->cb_regs[SocketState] & SE_POWER) + if (cb->regs[SocketState] & SE_POWER) engine(cb, CardPowered); - /* Enable interrupt on all events */ -// cb->cb_regs[SocketMask] |= 0xF; -// wrreg(cb, Rcscic, 0xC); + /* Ack and enable interrupts on all events */ + //cb->regs[SocketEvent] = cb->regs[SocketEvent]; + //cb->regs[SocketMask] |= 0xF; + //wrreg(cb, Rcscic, 0xC); } } static int -powerup(cb_t *cb) +powerup(Cardbus *cb) { ulong state; ushort bcr; - if ((state = cb->cb_regs[SocketState]) & SS_PC16) { + state = cb->regs[SocketState]; + if (state & SS_PC16) { // print("#Y%ld: Probed a PC16 card, powering up card\n", cb - cbslots); - cb->cb_type = PC16; - memset(&cb->cb_linfo, 0, sizeof(pcminfo_t)); + cb->type = PC16; + memset(&cb->linfo, 0, sizeof(Pcminfo)); /* power up and unreset, wait's are empirical (???) */ wrreg(cb, Rpc, Fautopower|Foutena|Fcardena); @@ -701,104 +582,111 @@ powerup(cb_t *cb) wrreg(cb, Rigc, 0); delay(100); wrreg(cb, Rigc, Fnotreset); + delay(500); return 1; } - if (cb->cb_regs[SocketState] & SS_CCD) + if (state & SS_CCD) return 0; - if ((state & SS_CBC) == 0 || (state & SS_NOTCARD)) { - print("#Y%ld: No cardbus card inserted\n", cb - cbslots); + if (state & SS_NOTCARD) { + print("#Y%ld: No card inserted\n", cb - cbslots); return 0; } if (state & SS_BADVCC) { print("#Y%ld: Bad VCC request to card, powering down card!\n", cb - cbslots); - cb->cb_regs[SocketControl] = 0; + cb->regs[SocketControl] = 0; return 0; } if ((state & SS_3V) == 0 && (state & SS_5V) == 0) { print("#Y%ld: Unsupported voltage, powering down card!\n", cb - cbslots); - cb->cb_regs[SocketControl] = 0; + cb->regs[SocketControl] = 0; return 0; } - print("#Y%ld: card %spowered at %d volt\n", cb - cbslots, - (state & SS_POWER)? "": "not ", - (state & SS_3V)? 3: (state & SS_5V)? 5: -1); + //print("#Y%ld: card %spowered at %d volt\n", cb - cbslots, + // (state & SS_POWER)? "": "not ", + // (state & SS_3V)? 3: (state & SS_5V)? 5: -1); /* Power up the card * and make sure the secondary bus is not in reset. */ - cb->cb_regs[SocketControl] = (state & SS_5V)? SC_5V: SC_3V; + cb->regs[SocketControl] = (state & SS_5V)? SC_5V: SC_3V; delay(50); - bcr = pcicfgr16(cb->cb_pci, PciBCR); + bcr = pcicfgr16(cb->pci, PciBCR); bcr &= ~0x40; - pcicfgw16(cb->cb_pci, PciBCR, bcr); + pcicfgw16(cb->pci, PciBCR, bcr); delay(100); - cb->cb_type = PC32; + cb->type = PC32; return 1; } static void -powerdown(cb_t *cb) +powerdown(Cardbus *cb) { ushort bcr; - if (cb->cb_type == PC16) { + if (cb->type == PC16) { wrreg(cb, Rpc, 0); /* turn off card power */ wrreg(cb, Rwe, 0); /* no windows */ - cb->cb_type = -1; + cb->type = -1; return; } - bcr = pcicfgr16(cb->cb_pci, PciBCR); + bcr = pcicfgr16(cb->pci, PciBCR); bcr |= 0x40; - pcicfgw16(cb->cb_pci, PciBCR, bcr); - cb->cb_regs[SocketControl] = 0; - cb->cb_type = -1; + pcicfgw16(cb->pci, PciBCR, bcr); + cb->regs[SocketControl] = 0; + cb->type = -1; } static void -configure(cb_t *cb) +configure(Cardbus *cb) { - int i; Pcidev *pci; + ulong size, bar; + int i, ioindex, memindex, r; - // print("configuring slot %d (%s)\n", (int)(cb - cbslots), states[cb->cb_state]); - if (cb->cb_state == SlotConfigured) + //print("configuring slot %d (%s)\n", (int)(cb - cbslots), states[cb->state]); + if (cb->state == SlotConfigured) return; engine(cb, CardConfigured); delay(50); /* Emperically established */ - if (cb->cb_type == PC16) { + if (cb->type == PC16) { i82365configure(cb); return; } /* Scan the CardBus for new PCI devices */ - pciscan(pcicfgr8(cb->cb_pci, PciSBN), &cb->cb_pci->bridge); - pci = cb->cb_pci->bridge; + pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge); + pci = cb->pci->bridge; while (pci) { - ulong size, bar; - int memindex, ioindex; - - /* Treat the found device as an ordinary PCI card. It seems that the - CIS is not always present in CardBus cards. XXX, need to support - multifunction cards */ + r = pcicfgr16(pci, PciPCR); + r &= ~(PciPCR_IO|PciPCR_MEM); + pcicfgw16(pci, PciPCR, r); + + /* + * Treat the found device as an ordinary PCI card. + * It seems that the CIS is not always present in + * CardBus cards. + * XXX, need to support multifunction cards + */ memindex = ioindex = 0; for (i = 0; i != Nbars; i++) { - if (pci->mem[i].size == 0) continue; + if (pci->mem[i].size == 0) + continue; if (pci->mem[i].bar & 1) { // Allocate I/O space @@ -810,8 +698,8 @@ configure(cb_t *cb) pci->mem[i].bar = bar | 1; pcicfgw32(pci, PciBAR0 + i * sizeof(ulong), pci->mem[i].bar); - pcicfgw16(cb->cb_pci, PciCBIBR0 + ioindex * 8, bar); - pcicfgw16(cb->cb_pci, PciCBILR0 + ioindex * 8, + pcicfgw16(cb->pci, PciCBIBR0 + ioindex * 8, bar); + pcicfgw16(cb->pci, PciCBILR0 + ioindex * 8, bar + pci->mem[i].size - 1); //print("ioindex[%d] %.8uX (%d)\n", // ioindex, bar, pci->mem[i].size); @@ -828,15 +716,16 @@ configure(cb_t *cb) bar = upamalloc(0, pci->mem[i].size, BY2PG); pci->mem[i].bar = bar | (pci->mem[i].bar & 0x80); pcicfgw32(pci, PciBAR0 + i * sizeof(ulong), pci->mem[i].bar); - pcicfgw32(cb->cb_pci, PciCBMBR0 + memindex * 8, bar); - pcicfgw32(cb->cb_pci, PciCBMLR0 + memindex * 8, + pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, bar); + pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, bar + pci->mem[i].size - 1); - if (pci->mem[i].bar & 0x80) + if (pci->mem[i].bar & 0x80) { /* Enable prefetch */ - pcicfgw16(cb->cb_pci, PciBCR, - pcicfgr16(cb->cb_pci, PciBCR) | - (1 << (8 + memindex))); + r = pcicfgr16(cb->pci, PciBCR); + r |= 1 << (8 + memindex); + pcicfgw16(cb->pci, PciBCR, r); + } //print("memindex[%d] %.8uX (%d)\n", // memindex, bar, pci->mem[i].size); @@ -853,27 +742,29 @@ configure(cb_t *cb) pci->rom.size = size; pcicfgw32(pci, PciEBAR0, pci->rom.bar); - pcicfgw32(cb->cb_pci, PciCBMBR0 + memindex * 8, + pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, pci->rom.bar); - pcicfgw32(cb->cb_pci, PciCBMLR0 + memindex * 8, + pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, pci->rom.bar + pci->rom.size - 1); } } /* Set the basic PCI registers for the device */ - pcicfgw16(pci, PciPCR, - pcicfgr16(pci, PciPCR) | - PciPCR_IO|PciPCR_MEM|PciPCR_Master); - pcicfgw8(pci, PciCLS, 8); - pcicfgw8(pci, PciLTR, 64); + pci->pcr = pcicfgr16(pci, PciPCR); + pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master; + pci->cls = 8; + pci->ltr = 64; + pcicfgw16(pci, PciPCR, pci->pcr); + pcicfgw8(pci, PciCLS, pci->cls); + pcicfgw8(pci, PciLTR, pci->ltr); if (pcicfgr8(pci, PciINTP)) { - pci->intl = pcicfgr8(cb->cb_pci, PciINTL); + pci->intl = pcicfgr8(cb->pci, PciINTL); pcicfgw8(pci, PciINTL, pci->intl); /* Route interrupts to INTA#/B# */ - pcicfgw16(cb->cb_pci, PciBCR, - pcicfgr16(cb->cb_pci, PciBCR) & ~(1 << 7)); + pcicfgw16(cb->pci, PciBCR, + pcicfgr16(cb->pci, PciBCR) & ~(1 << 7)); } pci = pci->list; @@ -881,54 +772,53 @@ configure(cb_t *cb) } static void -unconfigure(cb_t *cb) +unconfigure(Cardbus *cb) { Pcidev *pci; - int i, ioindex, memindex; + int i, ioindex, memindex, r; - if (cb->cb_type == PC16) { + if (cb->type == PC16) { print("#Y%d: Don't know how to unconfigure a PC16 card\n", (int)(cb - cbslots)); - memset(&cb->cb_linfo, 0, sizeof(pcminfo_t)); + memset(&cb->linfo, 0, sizeof(Pcminfo)); return; } - pci = cb->cb_pci->bridge; + pci = cb->pci->bridge; if (pci == nil) return; /* Not configured */ - cb->cb_pci->bridge = nil; + cb->pci->bridge = nil; memindex = ioindex = 0; while (pci) { Pcidev *_pci; for (i = 0; i != Nbars; i++) { - if (pci->mem[i].size == 0) continue; + if (pci->mem[i].size == 0) + continue; if (pci->mem[i].bar & 1) { iofree(pci->mem[i].bar & ~1); - pcicfgw16(cb->cb_pci, PciCBIBR0 + ioindex * 8, + pcicfgw16(cb->pci, PciCBIBR0 + ioindex * 8, (ushort)-1); - pcicfgw16(cb->cb_pci, PciCBILR0 + ioindex * 8, 0); + pcicfgw16(cb->pci, PciCBILR0 + ioindex * 8, 0); ioindex++; continue; } upafree(pci->mem[i].bar & ~0xF, pci->mem[i].size); - pcicfgw32(cb->cb_pci, PciCBMBR0 + memindex * 8, - (ulong)-1); - pcicfgw32(cb->cb_pci, PciCBMLR0 + memindex * 8, 0); - pcicfgw16(cb->cb_pci, PciBCR, - pcicfgr16(cb->cb_pci, PciBCR) & - ~(1 << (8 + memindex))); + pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1); + pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0); + r = pcicfgr16(cb->pci, PciBCR); + r &= ~(1 << (8 + memindex)); + pcicfgw16(cb->pci, PciBCR, r); memindex++; } if (pci->rom.bar && memindex < 2) { upafree(pci->rom.bar & ~0xF, pci->rom.size); - pcicfgw32(cb->cb_pci, PciCBMBR0 + memindex * 8, - (ulong)-1); - pcicfgw32(cb->cb_pci, PciCBMLR0 + memindex * 8, 0); + pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1); + pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0); memindex++; } @@ -939,7 +829,7 @@ unconfigure(cb_t *cb) } static void -i82365configure(cb_t *cb) +i82365configure(Cardbus *cb) { int this; Cisdat cis; @@ -997,20 +887,21 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) { int i, irq; PCMconftab *ct, *et; - pcminfo_t *pi; - cb_t *cb; + Pcminfo *pi; + Cardbus *cb; uchar x, we, *p; cb = nil; for (i = 0; i != nslots; i++) { cb = &cbslots[i]; - qlock(cb); - if (cb->cb_state == SlotConfigured && - cb->cb_type == PC16 && - strstr(cb->cb_linfo.pi_verstr, idstr)) + lock(cb); + if (cb->state == SlotConfigured && + cb->type == PC16 && + !cb->special && + strstr(cb->linfo.verstr, idstr)) break; - qunlock(cb); + unlock(cb); } if (i == nslots) { @@ -1018,7 +909,7 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) return -1; } - pi = &cb->cb_linfo; + pi = &cb->linfo; /* * configure the PCMslot for IO. We assume very heavily that we can read @@ -1028,7 +919,7 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) if(irq == 2) irq = 9; - et = &pi->pi_ctab[pi->pi_nctab]; + et = &pi->ctab[pi->nctab]; ct = nil; for(i = 0; i < isa->nopt; i++){ int index; @@ -1037,28 +928,28 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) if(strncmp(isa->opt[i], "index=", 6)) continue; index = strtol(&isa->opt[i][6], &cp, 0); - if(cp == &isa->opt[i][6] || index >= pi->pi_nctab) { - qunlock(cb); + if(cp == &isa->opt[i][6] || index >= pi->nctab) { + unlock(cb); print("#Y%d: Cannot find index %d in conf table\n", (int)(cb - cbslots), index); return -1; } - ct = &pi->pi_ctab[index]; + ct = &pi->ctab[index]; } if(ct == nil){ PCMconftab *t; /* assume default is right */ - if(pi->pi_defctab) - ct = pi->pi_defctab; + if(pi->defctab) + ct = pi->defctab; else - ct = pi->pi_ctab; + ct = pi->ctab; /* try for best match */ if(ct->nio == 0 || ct->io[0].start != isa->port || ((1<<irq) & ct->irqs) == 0){ - for(t = pi->pi_ctab; t < et; t++) + for(t = pi->ctab; t < et; t++) if(t->nio && t->io[0].start == isa->port && ((1<<irq) & t->irqs)){ @@ -1067,14 +958,14 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) } } if(ct->nio == 0 || ((1<<irq) & ct->irqs) == 0){ - for(t = pi->pi_ctab; t < et; t++) + for(t = pi->ctab; t < et; t++) if(t->nio && ((1<<irq) & t->irqs)){ ct = t; break; } } if(ct->nio == 0){ - for(t = pi->pi_ctab; t < et; t++) + for(t = pi->ctab; t < et; t++) if(t->nio){ ct = t; break; @@ -1083,16 +974,18 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) } if(ct == et || ct->nio == 0) { - qunlock(cb); + unlock(cb); print("#Y%d: No configuration?\n", (int)(cb - cbslots)); return -1; } if(isa->port == 0 && ct->io[0].start == 0) { - qunlock(cb); + unlock(cb); print("#Y%d: No part or start address\n", (int)(cb - cbslots)); return -1; } + cb->special = 1; /* taken */ + /* route interrupts */ isa->irq = irq; wrreg(cb, Rigc, irq | Fnotreset | Fiocard); @@ -1134,16 +1027,16 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) wrreg(cb, Rwe, we); /* only touch Rconfig if it is present */ - if(pi->pi_conf_present & (1<<Rconfig)){ + if(pi->conf_present & (1<<Rconfig)){ PCMmap *m; /* Reset adapter */ - m = isamap(cb, pi->pi_conf_addr + Rconfig, 1, 1); - p = KADDR(m->isa + pi->pi_conf_addr + Rconfig - m->ca); + m = isamap(cb, pi->conf_addr + Rconfig, 1, 1); + p = KADDR(m->isa + pi->conf_addr + Rconfig - m->ca); /* set configuration and interrupt type */ x = ct->index; - if((ct->irqtype & 0x20) && ((ct->irqtype & 0x40)==0 || isa->irq>7)) + if((ct->irqtype & 0x20)/* && ((ct->irqtype & 0x40)==0 || isa->irq>7)*/) x |= Clevel; *p = x; delay(5); @@ -1151,20 +1044,21 @@ pccard_pcmspecial(char *idstr, ISAConf *isa) isaunmap(m); } - pi->pi_port = isa->port; - pi->pi_irq = isa->irq; - qunlock(cb); + pi->port = isa->port; + pi->irq = isa->irq; + unlock(cb); - print("#Y%d: %s irq %ld, port %lX\n", (int)(cb - cbslots), pi->pi_verstr, isa->irq, isa->port); + print("#Y%d: %s irq %ld, port %lX\n", (int)(cb - cbslots), pi->verstr, isa->irq, isa->port); return (int)(cb - cbslots); } static void pccard_pcmspecialclose(int slotno) { - cb_t *cb = &cbslots[slotno]; + Cardbus *cb = &cbslots[slotno]; wrreg(cb, Rwe, 0); /* no windows */ + cb->special = 0; } static int @@ -1176,7 +1070,7 @@ xcistuple(int slotno, int tuple, int subtuple, void *v, int nv, int attr) uchar *p; uchar type, link, n, c; int this, subtype; - cb_t *cb = &cbslots[slotno]; + Cardbus *cb = &cbslots[slotno]; m = isamap(cb, 0, 0, attr); if(m == 0) @@ -1222,260 +1116,16 @@ xcistuple(int slotno, int tuple, int subtuple, void *v, int nv, int attr) return -1; } -// static Chan* -// pccardattach(char *spec) -// { -// if (!managerstarted) { -// managerstarted = 1; -// kproc("cardbus", processevents, nil); -// } -// return devattach('Y', spec); -// } -// -//enum -//{ -// Qdir, -// Qctl, -// -// Nents = 1, -//}; -// -//#define SLOTNO(c) ((ulong)((c->qid.path>>8)&0xff)) -//#define TYPE(c) ((ulong)(c->qid.path&0xff)) -//#define QID(s,t) (((s)<<8)|(t)) -// -//static int -//pccardgen(Chan *c, char*, Dirtab *, int , int i, Dir *dp) -//{ -// int slotno; -// Qid qid; -// long len; -// int entry; -// -// if(i == DEVDOTDOT){ -// mkqid(&qid, Qdir, 0, QTDIR); -// devdir(c, qid, "#Y", 0, eve, 0555, dp); -// return 1; -// } -// -// len = 0; -// if(i >= Nents * nslots) return -1; -// slotno = i / Nents; -// entry = i % Nents; -// if (entry == 0) { -// qid.path = QID(slotno, Qctl); -// snprint(up->genbuf, sizeof up->genbuf, "cb%dctl", slotno); -// } -// else { -// /* Entries for memory regions. I'll implement them when -// needed. (pb) */ -// } -// qid.vers = 0; -// qid.type = QTFILE; -// devdir(c, qid, up->genbuf, len, eve, 0660, dp); -// return 1; -//} -// -//static Walkqid* -//pccardwalk(Chan *c, Chan *nc, char **name, int nname) -//{ -// return devwalk(c, nc, name, nname, 0, 0, pccardgen); -//} -// -//static int -//pccardstat(Chan *c, uchar *db, int n) -//{ -// return devstat(c, db, n, 0, 0, pccardgen); -//} -// -//static void -//increfp(cb_t *cb) -//{ -// qlock(&cb->cb_refslock); -// cb->cb_refs++; -// qunlock(&cb->cb_refslock); -//} -// -//static void -//decrefp(cb_t *cb) -//{ -// qlock(&cb->cb_refslock); -// cb->cb_refs--; -// qunlock(&cb->cb_refslock); -//} -// -//static Chan* -//pccardopen(Chan *c, int omode) -//{ -// if (c->qid.type & QTDIR){ -// if(omode != OREAD) -// error(Eperm); -// } else -// increfp(&cbslots[SLOTNO(c)]); -// c->mode = openmode(omode); -// c->flag |= COPEN; -// c->offset = 0; -// return c; -//} -// -//static void -//pccardclose(Chan *c) -//{ -// if(c->flag & COPEN) -// if((c->qid.type & QTDIR) == 0) -// decrefp(&cbslots[SLOTNO(c)]); -//} -// -//static long -//pccardread(Chan *c, void *a, long n, vlong offset) -//{ -// cb_t *cb; -// char *buf, *p, *e; -// -// switch(TYPE(c)){ -// case Qdir: -// return devdirread(c, a, n, 0, 0, pccardgen); -// -// case Qctl: -// buf = p = malloc(READSTR); -// buf[0] = 0; -// e = p + READSTR; -// -// cb = &cbslots[SLOTNO(c)]; -// qlock(cb); -// p = seprint(p, e, "slot %ld: %s; ", cb - cbslots, states[cb->cb_state]); -// -// switch (cb->cb_type) { -// case -1: -// seprint(p, e, "\n"); -// break; -// -// case PC32: -// if (cb->cb_pci->bridge) { -// Pcidev *pci = cb->cb_pci->bridge; -// int i; -// -// while (pci) { -// p = seprint(p, e, "%.4uX %.4uX; irq %d\n", -// pci->vid, pci->did, pci->intl); -// for (i = 0; i != Nbars; i++) -// if (pci->mem[i].size) -// p = seprint(p, e, -// "\tmem[%d] %.8uX (%.8uX)\n", -// i, pci->mem[i].bar, -// pci->mem[i].size); -// if (pci->rom.size) -// p = seprint(p, e, "\tROM %.8uX (%.8uX)\n", i, -// pci->rom.bar, pci->rom.size); -// pci = pci->list; -// } -// } -// break; -// -// case PC16: -// if (cb->cb_state == SlotConfigured) { -// pcminfo_t *pi = &cb->cb_linfo; -// -// p = seprint(p, e, "%s port %X; irq %d;\n", -// pi->pi_verstr, pi->pi_port, -// pi->pi_irq); -// for (n = 0; n != pi->pi_nctab; n++) { -// PCMconftab *ct; -// int i; -// -// ct = &pi->pi_ctab[n]; -// p = seprint(p, e, -// "\tconfiguration[%d] irqs %.4X; vpp %d, %d; %s\n", -// n, ct->irqs, ct->vpp1, ct->vpp2, -// (ct == pi->pi_defctab)? "(default);": ""); -// for (i = 0; i != ct->nio; i++) -// if (ct->io[i].len > 0) -// p = seprint(p, e, "\t\tio[%d] %.8lX %d\n", -// i, ct->io[i].start, ct->io[i].len); -// } -// } -// break; -// } -// qunlock(cb); -// -// n = readstr(offset, a, n, buf); -// free(buf); -// return n; -// } -// return 0; -//} -// -//static long -//pccardwrite(Chan *c, void *v, long n, vlong) -//{ -// Rune r; -// ulong n0; -// int i, nf; -// char buf[255], *field[Ncmd], *device; -// cb_t *cb; -// -// n0 = n; -// switch(TYPE(c)){ -// case Qctl: -// cb = &cbslots[SLOTNO(c)]; -// if(n > sizeof(buf)-1) n = sizeof(buf)-1; -// memmove(buf, v, n); -// buf[n] = '\0'; -// -// nf = getfields(buf, field, Ncmd, 1, " \t\n"); -// for (i = 0; i != nf; i++) { -// if (!strcmp(field[i], "down")) { -// -// if (i + 1 < nf && *field[i + 1] == '#') { -// device = field[++i]; -// device += chartorune(&r, device); -// if ((n = devno(r, 1)) >= 0 && devtab[n]->config) -// devtab[n]->config(0, device, nil); -// } -// qengine(cb, CardEjected); -// } -// else if (!strcmp(field[i], "power")) { -// if ((cb->cb_regs[SocketState] & SS_CCD) == 0) -// qengine(cb, CardDetected); -// } -// else -// error(Ebadarg); -// } -// break; -// } -// return n0 - n; -//} -// -//Dev pccarddevtab = { -// 'Y', -// "cardbus", -// -// devreset, -// devinit, -// pccardattach, -// pccardwalk, -// pccardstat, -// pccardopen, -// devcreate, -// pccardclose, -// pccardread, -// devbread, -// pccardwrite, -// devbwrite, -// devremove, -// devwstat, -//}; - static PCMmap * -isamap(cb_t *cb, ulong offset, int len, int attr) +isamap(Cardbus *cb, ulong offset, int len, int attr) { uchar we, bit; PCMmap *m, *nm; - pcminfo_t *pi; + Pcminfo *pi; int i; ulong e; - pi = &cb->cb_linfo; + pi = &cb->linfo; /* convert offset to granularity */ if(len <= 0) @@ -1488,7 +1138,7 @@ isamap(cb_t *cb, ulong offset, int len, int attr) we = rdreg(cb, Rwe); bit = 1; nm = 0; - for(m = pi->pi_mmap; m < &pi->pi_mmap[nelem(pi->pi_mmap)]; m++){ + for(m = pi->mmap; m < &pi->mmap[nelem(pi->mmap)]; m++){ if((we & bit)) if(m->attr == attr) if(offset >= m->ca && e <= m->cea){ @@ -1522,7 +1172,7 @@ isamap(cb_t *cb, ulong offset, int len, int attr) m->ca = offset; m->cea = m->ca + m->len; m->attr = attr; - i = m - pi->pi_mmap; + i = m - pi->mmap; bit = 1<<i; wrreg(cb, Rwe, we & ~bit); /* disable map before changing it */ wrreg(cb, MAP(i, Mbtmlo), m->isa>>Mshift); @@ -1550,17 +1200,17 @@ isaunmap(PCMmap* m) * reading and writing card registers */ static uchar -rdreg(cb_t *cb, int index) +rdreg(Cardbus *cb, int index) { - outb(cb->cb_lindex, cb->cb_lbase + index); - return inb(cb->cb_ldata); + outb(cb->lindex, cb->lbase + index); + return inb(cb->ldata); } static void -wrreg(cb_t *cb, int index, uchar val) +wrreg(Cardbus *cb, int index, uchar val) { - outb(cb->cb_lindex, cb->cb_lbase + index); - outb(cb->cb_ldata, val); + outb(cb->lindex, cb->lbase + index); + outb(cb->ldata, val); } static int @@ -1590,11 +1240,11 @@ getlong(Cisdat *cis, int size) } static void -tcfig(cb_t *cb, Cisdat *cis, int ) +tcfig(Cardbus *cb, Cisdat *cis, int ) { uchar size, rasize, rmsize; uchar last; - pcminfo_t *pi; + Pcminfo *pi; if(readc(cis, &size) != 1) return; @@ -1603,25 +1253,25 @@ tcfig(cb_t *cb, Cisdat *cis, int ) if(readc(cis, &last) != 1) return; - pi = &cb->cb_linfo; - pi->pi_conf_addr = getlong(cis, rasize); - pi->pi_conf_present = getlong(cis, rmsize); + pi = &cb->linfo; + pi->conf_addr = getlong(cis, rasize); + pi->conf_present = getlong(cis, rmsize); } static void -tvers1(cb_t *cb, Cisdat *cis, int ) +tvers1(Cardbus *cb, Cisdat *cis, int ) { uchar c, major, minor, last; int i; - pcminfo_t *pi; + Pcminfo *pi; - pi = &cb->cb_linfo; + pi = &cb->linfo; if(readc(cis, &major) != 1) return; if(readc(cis, &minor) != 1) return; last = 0; - for(i = 0; i < sizeof(pi->pi_verstr) - 1; i++){ + for(i = 0; i < sizeof(pi->verstr) - 1; i++){ if(readc(cis, &c) != 1) return; if(c == 0) @@ -1632,10 +1282,10 @@ tvers1(cb_t *cb, Cisdat *cis, int ) break; if(c == ';' && last == ';') continue; - pi->pi_verstr[i] = c; + pi->verstr[i] = c; last = c; } - pi->pi_verstr[i] = 0; + pi->verstr[i] = 0; } static ulong @@ -1740,10 +1390,10 @@ timing(Cisdat *cis, PCMconftab *ct) ct->maxwait = ttiming(cis, i); /* max wait */ i = (c>>2)&0x7; if(i != 7) - ct->readywait = ttiming(cis, i); /* max ready/busy wait */ + ct->readywait = ttiming(cis, i); /* max ready/busy wait */ i = (c>>5)&0x7; if(i != 7) - ct->otherwait = ttiming(cis, i); /* reserved wait */ + ct->otherwait = ttiming(cis, i); /* reserved wait */ } static void @@ -1809,28 +1459,28 @@ memspace(Cisdat *cis, int asize, int lsize, int host) } static void -tentry(cb_t *cb, Cisdat *cis, int ) +tentry(Cardbus *cb, Cisdat *cis, int ) { uchar c, i, feature; PCMconftab *ct; - pcminfo_t *pi; + Pcminfo *pi; - pi = &cb->cb_linfo; - if(pi->pi_nctab >= nelem(pi->pi_ctab)) + pi = &cb->linfo; + if(pi->nctab >= nelem(pi->ctab)) return; if(readc(cis, &c) != 1) return; - ct = &pi->pi_ctab[pi->pi_nctab++]; + ct = &pi->ctab[pi->nctab++]; /* copy from last default config */ - if(pi->pi_defctab) - *ct = *pi->pi_defctab; + if(pi->defctab) + *ct = *pi->defctab; ct->index = c & 0x3f; /* is this the new default? */ if(c & 0x40) - pi->pi_defctab = ct; + pi->defctab = ct; /* memory wait specified? */ if(c & 0x80){ @@ -1881,7 +1531,7 @@ tentry(cb_t *cb, Cisdat *cis, int ) } static void -i82365probe(cb_t *cb, int lindex, int ldata) +i82365probe(Cardbus *cb, int lindex, int ldata) { uchar c, id; int dev = 0; /* According to the Ricoh spec 00->3F _and_ 80->BF seem @@ -1894,51 +1544,51 @@ i82365probe(cb_t *cb, int lindex, int ldata) if((id & 0x0f) == 0x00) return; /* no revision number, not possible */ - cb->cb_lindex = lindex; - cb->cb_ldata = ldata; - cb->cb_ltype = Ti82365; - cb->cb_lbase = (int)(cb - cbslots) * 0x40; + cb->lindex = lindex; + cb->ldata = ldata; + cb->ltype = Ti82365; + cb->lbase = (int)(cb - cbslots) * 0x40; switch(id){ case 0x82: case 0x83: case 0x84: /* could be a cirrus */ - outb(cb->cb_lindex, Rchipinfo + (dev<<7)); - outb(cb->cb_ldata, 0); - c = inb(cb->cb_ldata); + outb(cb->lindex, Rchipinfo + (dev<<7)); + outb(cb->ldata, 0); + c = inb(cb->ldata); if((c & 0xc0) != 0xc0) break; - c = inb(cb->cb_ldata); + c = inb(cb->ldata); if((c & 0xc0) != 0x00) break; if(c & 0x20){ - cb->cb_ltype = Tpd6720; + cb->ltype = Tpd6720; } else { - cb->cb_ltype = Tpd6710; + cb->ltype = Tpd6710; } break; } /* if it's not a Cirrus, it could be a Vadem... */ - if(cb->cb_ltype == Ti82365){ + if(cb->ltype == Ti82365){ /* unlock the Vadem extended regs */ - outb(cb->cb_lindex, 0x0E + (dev<<7)); - outb(cb->cb_lindex, 0x37 + (dev<<7)); + outb(cb->lindex, 0x0E + (dev<<7)); + outb(cb->lindex, 0x37 + (dev<<7)); /* make the id register show the Vadem id */ - outb(cb->cb_lindex, 0x3A + (dev<<7)); - c = inb(cb->cb_ldata); - outb(cb->cb_ldata, c|0xC0); - outb(cb->cb_lindex, Rid + (dev<<7)); - c = inb(cb->cb_ldata); + outb(cb->lindex, 0x3A + (dev<<7)); + c = inb(cb->ldata); + outb(cb->ldata, c|0xC0); + outb(cb->lindex, Rid + (dev<<7)); + c = inb(cb->ldata); if(c & 0x08) - cb->cb_ltype = Tvg46x; + cb->ltype = Tvg46x; /* go back to Intel compatible id */ - outb(cb->cb_lindex, 0x3A + (dev<<7)); - c = inb(cb->cb_ldata); - outb(cb->cb_ldata, c & ~0xC0); + outb(cb->lindex, 0x3A + (dev<<7)); + c = inb(cb->ldata); + outb(cb->ldata, c & ~0xC0); } } @@ -1954,4 +1604,3 @@ vcode(int volt) return 0; } } - diff --git a/os/boot/pc/devsd.c b/os/boot/pc/devsd.c index 54bfd835..87df96b4 100644 --- a/os/boot/pc/devsd.c +++ b/os/boot/pc/devsd.c @@ -32,13 +32,13 @@ enum { }; void -sdaddpart(SDunit* unit, char* name, ulong start, ulong end) +sdaddpart(SDunit* unit, char* name, uvlong start, uvlong end) { SDpart *pp; int i, partno; if(parttrace) - print("add %d %s %s %ld %ld\n", unit->npart, unit->name, name, start, end); + print("add %d %s %s %lld %lld\n", unit->npart, unit->name, name, start, end); /* * Check name not already used * and look for a free slot. @@ -73,7 +73,7 @@ sdaddpart(SDunit* unit, char* name, ulong start, ulong end) * Check there is a free slot and size and extent are valid. */ if(partno == -1 || start > end || end > unit->sectors){ - print("cannot add %s!%s [%lud,%lud) to disk [0,%lud): %s\n", + print("cannot add %s!%s [%llud,%llud) to disk [0,%llud): %s\n", unit->name, name, start, end, unit->sectors, partno==-1 ? "no free partitions" : "partition boundaries out of range"); return; @@ -224,6 +224,19 @@ _sddetach(void) } } +static void +sddump(void) +{ + SDev *sdev; + + print("sdevs:\n"); + for(sdev = sdlist; sdev != nil; sdev = sdev->next){ + print("sdev %c index %d nunit %d: ", + sdev->idno, sdev->index, sdev->nunit); + print("\n"); + } +} + static int _sdinit(void) { @@ -247,13 +260,12 @@ _sdinit(void) else sdlist = sdev; for(tail = sdev; tail->next != nil; tail = tail->next){ - sdev->index = sdnunit; + tail->index = sdnunit; sdnunit += tail->nunit; } tail->index = sdnunit; sdnunit += tail->nunit; } - /* * Legacy and option code goes here. This will be hard... */ @@ -274,6 +286,8 @@ _sdinit(void) if(sdifc[i]->id) sdifc[i]->id(sdlist); } + if (0) + sddump(); m = 0; cdmask = sdmask = 0; @@ -448,7 +462,7 @@ sdaddconf(int i) addconf("%spart=", unit->name); for(i=1, pp=&unit->part[i]; i<unit->npart; i++, pp++) /* skip 0, which is "data" */ - addconf("%s%s %ld %ld", i==1 ? "" : "/", pp->name, + addconf("%s%s %lld %lld", i==1 ? "" : "/", pp->name, pp->start, pp->end); addconf("\n"); } diff --git a/os/boot/pc/ether.c b/os/boot/pc/ether.c index c8a4b7de..90bdcb5f 100644 --- a/os/boot/pc/ether.c +++ b/os/boot/pc/ether.c @@ -14,6 +14,7 @@ extern int ether2114xreset(Ether*); extern int elnk3reset(Ether*); extern int i82557reset(Ether*); extern int igbepnp(Ether *); +extern int i82563pnp(Ether *); extern int elnk3reset(Ether*); extern int ether589reset(Ether*); extern int ne2000reset(Ether*); @@ -24,6 +25,8 @@ extern int rtl8139pnp(Ether*); extern int rtl8169pnp(Ether*); extern int ether83815reset(Ether*); extern int rhinepnp(Ether*); +extern int ga620pnp(Ether*); +extern int dp83820pnp(Ether*); struct { char *type; @@ -34,6 +37,8 @@ struct { { "2114x", ether2114xreset, 0, }, { "i82557", i82557reset, 0, }, { "igbe", igbepnp, 0, }, + { "i82563",i82563pnp, 0, }, + { "igbepcie",i82563pnp, 0, }, { "elnk3", elnk3reset, 0, }, { "3C509", elnk3reset, 0, }, { "3C575", elnk3reset, 0, }, @@ -48,6 +53,10 @@ struct { { "RTL8169", rtl8169pnp, 0, }, { "83815", ether83815reset, 0, }, { "rhine", rhinepnp, 0, }, + { "vt6102", rhinepnp, 0, }, + { "GA620", ga620pnp, 0, }, + { "83820", dp83820pnp, 0, }, + { "dp83820", dp83820pnp, 0, }, { 0, } }; @@ -90,7 +99,7 @@ etherinit(void) continue; } - ctlr->state = 1; + ctlr->state = 1; /* card found */ mask |= 1<<ctlrno; if(ctlr->irq == 2) ctlr->irq = 9; @@ -150,8 +159,8 @@ attach(int ctlrno) return 0; ctlr = ðer[ctlrno]; - if(ctlr->state == 1){ - ctlr->state = 2; + if(ctlr->state == 1){ /* card found? */ + ctlr->state = 2; /* attaching */ (*ctlr->attach)(ctlr); } @@ -167,7 +176,7 @@ xetherdetach(void) x = splhi(); for(ctlrno = 0; ctlrno < MaxEther; ctlrno++){ ctlr = ðer[ctlrno]; - if(ctlr->detach && ctlr->state != 0) + if(ctlr->detach && ctlr->state != 0) /* found | attaching? */ ctlr->detach(ctlr); } splx(x); diff --git a/os/boot/pc/ether589.c b/os/boot/pc/ether589.c index fc86f463..d9923062 100644 --- a/os/boot/pc/ether589.c +++ b/os/boot/pc/ether589.c @@ -155,7 +155,7 @@ if(debug) print("none found\n"); if(memcmp(ea, ether->ea, 6) == 0 && strcmp(type, "3C562") == 0) { if(debug) print("read 562..."); - if(pcmcistuple(slot, 0x88, ea, 6) == 6) { + if(pcmcistuple(slot, 0x88, -1, ea, 6) == 6) { for(i = 0; i < 6; i += 2){ t = ea[i]; ea[i] = ea[i+1]; diff --git a/os/boot/pc/ether8169.c b/os/boot/pc/ether8169.c index 5b36f7c3..009dfcde 100644 --- a/os/boot/pc/ether8169.c +++ b/os/boot/pc/ether8169.c @@ -17,13 +17,10 @@ #include "fns.h" #include "io.h" - typedef struct QLock { int r; } QLock; #define qlock(i) while(0) #define qunlock(i) while(0) #define iallocb allocb -extern void mb386(void); -#define coherence() mb386() #define iprint print #define mallocalign(n, a, o, s) ialloc((n), (a)) @@ -108,6 +105,16 @@ enum { /* Tcr */ Ifg2 = 0x00080000, /* Interframe Gap 2 */ HwveridSHIFT = 23, /* Hardware Version ID */ HwveridMASK = 0x7C800000, + Macv01 = 0x00000000, /* RTL8169 */ + Macv02 = 0x00800000, /* RTL8169S/8110S */ + Macv03 = 0x04000000, /* RTL8169S/8110S */ + Macv04 = 0x10000000, /* RTL8169SB/8110SB */ + Macv05 = 0x18000000, /* RTL8169SC/8110SC */ + Macv11 = 0x30000000, /* RTL8168B/8111B */ + Macv12 = 0x38000000, /* RTL8169B/8111B */ + Macv13 = 0x34000000, /* RTL8101E */ + Macv14 = 0x30800000, /* RTL8100E */ + Macv15 = 0x38800000, /* RTL8100E */ Ifg0 = 0x01000000, /* Interframe Gap 0 */ Ifg1 = 0x02000000, /* Interframe Gap 1 */ }; @@ -236,18 +243,31 @@ struct Dtcc { u16int txundrn; }; +enum { /* Variants */ + Rtl8100e = (0x8136<<16)|0x10EC, /* RTL810[01]E ? */ + Rtl8169c = (0x0116<<16)|0x16EC, /* RTL8169C+ (USR997902) */ + Rtl8169sc = (0x8167<<16)|0x10EC, /* RTL8169SC */ + Rtl8168b = (0x8168<<16)|0x10EC, /* RTL8168B */ + Rtl8169 = (0x8169<<16)|0x10EC, /* RTL8169 */ +}; + typedef struct Ctlr Ctlr; typedef struct Ctlr { int port; Pcidev* pcidev; Ctlr* next; int active; - uint id; + + void* nic; QLock alock; /* attach */ Lock ilock; /* init */ int init; /* */ + int pciv; /* */ + int macv; /* MAC version */ + int phyv; /* PHY version */ + Mii* mii; Lock tlock; /* transmit */ @@ -287,8 +307,8 @@ typedef struct Ctlr { uint fovw; } Ctlr; -static Ctlr* ctlrhead; -static Ctlr* ctlrtail; +static Ctlr* rtl8169ctlrhead; +static Ctlr* rtl8169ctlrtail; #define csr8r(c, r) (inb((c)->port+(r))) #define csr16r(c, r) (ins((c)->port+(r))) @@ -360,36 +380,59 @@ rtl8169mii(Ctlr* ctlr) ctlr->mii->mir = rtl8169miimir; ctlr->mii->miw = rtl8169miimiw; ctlr->mii->ctlr = ctlr; - rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */ - if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){ + /* + * Get rev number out of Phyidr2 so can config properly. + * There's probably more special stuff for Macv0[234] needed here. + */ + ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F; + if(ctlr->macv == Macv02){ + csr8w(ctlr, 0x82, 1); /* magic */ + rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */ + } + + if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){ free(ctlr->mii); ctlr->mii = nil; return -1; } - print("oui %X phyno %d\n", phy->oui, phy->phyno); + print("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n", + phy->oui, phy->phyno, ctlr->macv, ctlr->phyv); miiane(ctlr->mii, ~0, ~0, ~0); return 0; } +static void +rtl8169halt(Ctlr* ctlr) +{ + csr8w(ctlr, Cr, 0); + csr16w(ctlr, Imr, 0); + csr16w(ctlr, Isr, ~0); +} + static int rtl8169reset(Ctlr* ctlr) { + u32int r; int timeo; /* * Soft reset the controller. */ csr8w(ctlr, Cr, Rst); - for(timeo = 0; timeo < 1000; timeo++){ - if(!(csr8r(ctlr, Cr) & Rst)) - return 0; + for(r = timeo = 0; timeo < 1000; timeo++){ + r = csr8r(ctlr, Cr); + if(!(r & Rst)) + break; delay(1); } + rtl8169halt(ctlr); - return -1; + if(r & Rst) + return -1; + return 0; } static void @@ -399,14 +442,6 @@ rtl8169detach(Ether* edev) } static void -rtl8169halt(Ctlr* ctlr) -{ - csr8w(ctlr, Cr, 0); - csr16w(ctlr, Imr, 0); - csr16w(ctlr, Isr, ~0); -} - -static void rtl8169replenish(Ctlr* ctlr) { D *d; @@ -420,7 +455,7 @@ rtl8169replenish(Ctlr* ctlr) /* * simple allocation for now */ - bp = malloc(Mps); + bp = mallocalign(Mps, 8, 0, 0); ctlr->rb[rdt] = bp; d->addrlo = PCIWADDR(bp); d->addrhi = 0; @@ -433,11 +468,12 @@ rtl8169replenish(Ctlr* ctlr) ctlr->rdt = rdt; } -static void +static int rtl8169init(Ether* edev) { - uint r; + u32int r; Ctlr *ctlr; + u8int cplusc; ctlr = edev->ctlr; ilock(&ctlr->ilock); @@ -445,12 +481,6 @@ rtl8169init(Ether* edev) rtl8169halt(ctlr); /* - * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst settings - * in Tcr/Rcr. - */ - csr16w(ctlr, Cplusc, (1<<14)|Rxchksum|Mulrw); /* magic (1<<14) */ - - /* * MAC Address. * Must put chip into config register write enable mode. */ @@ -461,45 +491,95 @@ rtl8169init(Ether* edev) csr32w(ctlr, Idr0+4, r); /* - * Enable receiver/transmitter. - * Need to do this first or some of the settings below - * won't take. - */ - csr8w(ctlr, Cr, Te|Re); - - /* * Transmitter. - * Mtps is in units of 128. */ memset(ctlr->td, 0, sizeof(D)*ctlr->ntd); ctlr->tdh = ctlr->tdt = 0; ctlr->td[ctlr->ntd-1].control = Eor; - ctlr->mtps = HOWMANY(Mps, 128); /* * Receiver. + * Need to do something here about the multicast filter. */ memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd); ctlr->rdh = ctlr->rdt = 0; ctlr->rd[ctlr->nrd-1].control = Eor; - - //for(i = 0; i < ctlr->nrd; i++){ - // if((bp = ctlr->rb[i]) != nil){ - // ctlr->rb[i] = nil; - // freeb(bp); - // } - //} rtl8169replenish(ctlr); - ctlr->rcr = Rxfth256|Mrxdmaunlimited|Ab|Apm; + ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Apm; + + /* + * Mtps is in units of 128 except for the RTL8169 + * where is is 32. If using jumbo frames should be + * set to 0x3F. + * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst + * settings in Tcr/Rcr; the (1<<14) is magic. + */ + ctlr->mtps = HOWMANY(Mps, 128); + cplusc = csr16r(ctlr, Cplusc) & ~(1<<14); + cplusc |= Rxchksum|Mulrw; + switch(ctlr->macv){ + default: + return -1; + case Macv01: + ctlr->mtps = HOWMANY(Mps, 32); + break; + case Macv02: + case Macv03: + cplusc |= (1<<14); /* magic */ + break; + case Macv05: + /* + * This is interpreted from clearly bogus code + * in the manufacturer-supplied driver, it could + * be wrong. Untested. + */ + r = csr8r(ctlr, Config2) & 0x07; + if(r == 0x01) /* 66MHz PCI */ + csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */ + else + csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */ + pciclrmwi(ctlr->pcidev); + break; + case Macv13: + /* + * This is interpreted from clearly bogus code + * in the manufacturer-supplied driver, it could + * be wrong. Untested. + */ + pcicfgw8(ctlr->pcidev, 0x68, 0x00); /* magic */ + pcicfgw8(ctlr->pcidev, 0x69, 0x08); /* magic */ + break; + case Macv04: + case Macv11: + case Macv12: + case Macv14: + case Macv15: + break; + } + + /* + * Enable receiver/transmitter. + * Need to do this first or some of the settings below + * won't take. + */ + switch(ctlr->pciv){ + default: + csr8w(ctlr, Cr, Te|Re); + csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited); + csr32w(ctlr, Rcr, ctlr->rcr); + case Rtl8169sc: + case Rtl8168b: + break; + } /* * Interrupts. * Disable Tdu|Tok for now, the transmit routine will tidy. - * Tdu means the NIC ran out of descritors to send, so it + * Tdu means the NIC ran out of descriptors to send, so it * doesn't really need to ever be on. */ csr32w(ctlr, Timerint, 0); - csr16w(ctlr, Imr, Serr|Timeout/*|Tdu*/|Fovw|Punlc|Rdu|Ter/*|Tok*/|Rer|Rok); + csr16w(ctlr, Imr, Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok); /* * Clear missed-packet counter; @@ -515,20 +595,41 @@ rtl8169init(Ether* edev) csr32w(ctlr, Rdsar+4, 0); csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd)); csr16w(ctlr, Rms, Mps); - csr16w(ctlr, Mulint, 0); + r = csr16r(ctlr, Mulint) & 0xF000; + csr16w(ctlr, Mulint, r); + csr16w(ctlr, Cplusc, cplusc); /* * Set configuration. */ - csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited); - csr32w(ctlr, Rcr, ctlr->rcr); - csr16w(ctlr, 0xE2, 0); /* magic */ + switch(ctlr->pciv){ + default: + break; + case Rtl8169sc: + csr16w(ctlr, 0xE2, 0); /* magic */ + csr8w(ctlr, Cr, Te|Re); + csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited); + csr32w(ctlr, Rcr, ctlr->rcr); + break; + case Rtl8168b: + case Rtl8169c: + csr16w(ctlr, 0xE2, 0); /* magic */ + csr16w(ctlr, Cplusc, 0x2000); /* magic */ + csr8w(ctlr, Cr, Te|Re); + csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited); + csr32w(ctlr, Rcr, ctlr->rcr); + csr16w(ctlr, Rms, 0x0800); + csr8w(ctlr, Mtps, 0x3F); + break; + } csr8w(ctlr, Cr9346, 0); iunlock(&ctlr->ilock); - //rtl8169mii(ctlr); +// rtl8169mii(ctlr); + + return 0; } static void @@ -665,7 +766,7 @@ rtl8169receive(Ether* edev) else{ /* * Error stuff here. - print("control %8.8uX\n", control); + print("control %#8.8ux\n", control); */ } d->control &= Eor; @@ -688,7 +789,7 @@ rtl8169interrupt(Ureg*, void* arg) edev = arg; ctlr = edev->ctlr; - while((isr = csr16r(ctlr, Isr)) != 0){ + while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){ csr16w(ctlr, Isr, isr); if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){ rtl8169receive(edev); @@ -711,7 +812,7 @@ rtl8169interrupt(Ureg*, void* arg) } if(isr & Punlc){ - //rtl8169link(edev); +// rtl8169link(edev); isr &= ~Punlc; } @@ -719,104 +820,104 @@ rtl8169interrupt(Ureg*, void* arg) * Some of the reserved bits get set sometimes... */ if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok)) - panic("rtl8169interrupt: imr %4.4uX isr %4.4uX\n", + panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux\n", csr16r(ctlr, Imr), isr); } } -static Ctlr* -rtl8169match(Ether* edev, int id) +static void +rtl8169pci(void) { Pcidev *p; Ctlr *ctlr; - int port; + int i, port; + u32int bar; - /* - * Any adapter matches if no edev->port is supplied, - * otherwise the ports must match. - */ - for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){ - if(ctlr->active) + p = nil; + while(p = pcimatch(p, 0, 0)){ + if(p->ccrb != 0x02 || p->ccru != 0) continue; - p = ctlr->pcidev; - if(((p->did<<16)|p->vid) != id) - continue; - port = p->mem[0].bar & ~0x01; - if(edev->port != 0 && edev->port != port) + + switch(i = ((p->did<<16)|p->vid)){ + default: continue; + case Rtl8100e: /* RTL810[01]E ? */ + case Rtl8169c: /* RTL8169C */ + case Rtl8169sc: /* RTL8169SC */ + case Rtl8168b: /* RTL8168B */ + case Rtl8169: /* RTL8169 */ + break; + case (0xC107<<16)|0x1259: /* Corega CG-LAPCIGT */ + i = Rtl8169; + break; + } + bar = p->mem[0].bar; + port = bar & ~0x01; + if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){ + print("rtl8169: port %#ux in use\n", port); + continue; + } + ctlr = malloc(sizeof(Ctlr)); ctlr->port = port; - if(rtl8169reset(ctlr)) + ctlr->pcidev = p; + ctlr->pciv = i; + + if(pcigetpms(p) > 0){ + pcisetpms(p, 0); + + for(i = 0; i < 6; i++) + pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar); + pcicfgw8(p, PciINTL, p->intl); + pcicfgw8(p, PciLTR, p->ltr); + pcicfgw8(p, PciCLS, p->cls); + pcicfgw16(p, PciPCR, p->pcr); + } + + if(rtl8169reset(ctlr)){ + iofree(port); + free(ctlr); continue; + } - csr8w(ctlr, 0x82, 1); /* magic */ + /* + * Extract the chip hardware version, + * needed to configure each properly. + */ + ctlr->macv = csr32r(ctlr, Tcr) & HwveridMASK; rtl8169mii(ctlr); pcisetbme(p); - ctlr->active = 1; - return ctlr; + + if(rtl8169ctlrhead != nil) + rtl8169ctlrtail->next = ctlr; + else + rtl8169ctlrhead = ctlr; + rtl8169ctlrtail = ctlr; } - return nil; } -static struct { - char* name; - int id; -} rtl8169pci[] = { - { "rtl8169", (0x8169<<16)|0x10EC, }, /* generic */ - { "CG-LAPCIGT", (0xC107<<16)|0x1259, }, /* Corega CG-LAPCIGT */ - { nil }, -}; - int rtl8169pnp(Ether* edev) { - Pcidev *p; + u32int r; Ctlr *ctlr; - int i, id; - uchar ea[Eaddrlen]; - /* - * Make a list of all ethernet controllers - * if not already done. - */ - if(ctlrhead == nil){ - p = nil; - while(p = pcimatch(p, 0, 0)){ - if(p->ccrb != 0x02 || p->ccru != 0) - continue; - ctlr = malloc(sizeof(Ctlr)); - ctlr->pcidev = p; - ctlr->id = (p->did<<16)|p->vid; - - if(ctlrhead != nil) - ctlrtail->next = ctlr; - else - ctlrhead = ctlr; - ctlrtail = ctlr; - } - } + if(rtl8169ctlrhead == nil) + rtl8169pci(); /* - * Is it an RTL8169 under a different name? - * Normally a search is made through all the found controllers - * for one which matches any of the known vid+did pairs. - * If a vid+did pair is specified a search is made for that - * specific controller only. + * Any adapter matches if no edev->port is supplied, + * otherwise the ports must match. */ - id = 0; - for(i = 0; i < edev->nopt; i++){ - if(cistrncmp(edev->opt[i], "id=", 3) == 0) - id = strtol(&edev->opt[i][3], nil, 0); - } - - ctlr = nil; - if(id != 0) - ctlr = rtl8169match(edev, id); - else for(i = 0; rtl8169pci[i].name; i++){ - if((ctlr = rtl8169match(edev, rtl8169pci[i].id)) != nil) + for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){ + if(ctlr->active) + continue; + if(edev->port == 0 || edev->port == ctlr->port){ + ctlr->active = 1; break; + } } if(ctlr == nil) return -1; @@ -825,23 +926,33 @@ rtl8169pnp(Ether* edev) edev->port = ctlr->port; edev->irq = ctlr->pcidev->intl; edev->tbdf = ctlr->pcidev->tbdf; +// edev->mbps = 100; /* + * Pull the MAC address out of the chip. */ - memset(ea, 0, Eaddrlen); - i = csr32r(ctlr, Idr0); - edev->ea[0] = i; - edev->ea[1] = i>>8; - edev->ea[2] = i>>16; - edev->ea[3] = i>>24; - i = csr32r(ctlr, Idr0+4); - edev->ea[4] = i; - edev->ea[5] = i>>8; + r = csr32r(ctlr, Idr0); + edev->ea[0] = r; + edev->ea[1] = r>>8; + edev->ea[2] = r>>16; + edev->ea[3] = r>>24; + r = csr32r(ctlr, Idr0+4); + edev->ea[4] = r; + edev->ea[5] = r>>8; + /* + * Linkage to the generic ethernet driver. + */ edev->attach = rtl8169attach; edev->transmit = rtl8169transmit; edev->interrupt = rtl8169interrupt; edev->detach = rtl8169detach; +// edev->ifstat = rtl8169ifstat; +// edev->ctl = nil; +// +// edev->arg = edev; +// edev->promiscuous = rtl8169promiscuous; +// edev->multicast = rtl8169multicast; return 0; } diff --git a/os/boot/pc/ether82557.c b/os/boot/pc/ether82557.c index 1876692c..cba1f515 100644 --- a/os/boot/pc/ether82557.c +++ b/os/boot/pc/ether82557.c @@ -553,12 +553,13 @@ i82557pci(void) continue; case 0x1031: /* Intel 82562EM */ case 0x1050: /* Intel 82562EZ */ + case 0x1039: /* Intel 82801BD PRO/100 VE */ + case 0x103A: /* Intel 82562 PRO/100 VE */ + case 0x1064: /* Intel 82562 PRO/100 VE */ case 0x2449: /* Intel 82562ET */ case 0x1209: /* Intel 82559ER */ case 0x1229: /* Intel 8255[789] */ case 0x1030: /* Intel 82559 InBusiness 10/100 */ - case 0x1039: /* Intel 82801BD PRO/100 VE */ - case 0x103A: /* Intel 82562 PRO/100 VE */ break; } diff --git a/os/boot/pc/ether82563.c b/os/boot/pc/ether82563.c new file mode 100644 index 00000000..dfe2b4d3 --- /dev/null +++ b/os/boot/pc/ether82563.c @@ -0,0 +1,977 @@ +/* + * bootstrap driver for + * Intel 82563, 82571, 82573 Gigabit Ethernet PCI-Express Controllers + */ +#include "u.h" +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" + +#include "etherif.h" + +/* compatibility with cpu kernels */ +#define iallocb allocb +#ifndef CACHELINESZ +#define CACHELINESZ 32 /* pentium & later */ +#endif + +/* from pci.c */ +enum +{ /* command register pcidev->pcr */ + IOen = 1<<0, + MEMen = 1<<1, + MASen = 1<<2, + MemWrInv = 1<<4, + PErrEn = 1<<6, + SErrEn = 1<<8, +}; + +/* + * these are in the order they appear in the manual, not numeric order. + * It was too hard to find them in the book. Ref 21489, rev 2.6 + */ + +enum { + /* General */ + + Ctrl = 0x00000000, /* Device Control */ + Status = 0x00000008, /* Device Status */ + Eec = 0x00000010, /* EEPROM/Flash Control/Data */ + Eerd = 0x00000014, /* EEPROM Read */ + Ctrlext = 0x00000018, /* Extended Device Control */ + Fla = 0x0000001c, /* Flash Access */ + Mdic = 0x00000020, /* MDI Control */ + Seresctl = 0x00000024, /* Serdes ana */ + Fcal = 0x00000028, /* Flow Control Address Low */ + Fcah = 0x0000002C, /* Flow Control Address High */ + Fct = 0x00000030, /* Flow Control Type */ + Kumctrlsta = 0x00000034, /* Kumeran Controll and Status Register */ + Vet = 0x00000038, /* VLAN EtherType */ + Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */ + Txcw = 0x00000178, /* Transmit Configuration Word */ + Rxcw = 0x00000180, /* Receive Configuration Word */ + Ledctl = 0x00000E00, /* LED control */ + Pba = 0x00001000, /* Packet Buffer Allocation */ + + /* Interrupt */ + + Icr = 0x000000C0, /* Interrupt Cause Read */ + Ics = 0x000000C8, /* Interrupt Cause Set */ + Ims = 0x000000D0, /* Interrupt Mask Set/Read */ + Imc = 0x000000D8, /* Interrupt mask Clear */ + Iam = 0x000000E0, /* Interrupt acknowledge Auto Mask */ + + /* Receive */ + + Rctl = 0x00000100, /* Receive Control */ + Ert = 0x00002008, /* Early Receive Threshold (573[EVL] only) */ + Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */ + Fcrth = 0x00002168, /* Flow Control Rx Threshold High */ + Psrctl = 0x00002170, /* Packet Split Receive Control */ + Rdbal = 0x00002800, /* Rdesc Base Address Low Queue 0 */ + Rdbah = 0x00002804, /* Rdesc Base Address High Queue 0 */ + Rdlen = 0x00002808, /* Receive Descriptor Length Queue 0 */ + Rdh = 0x00002810, /* Receive Descriptor Head Queue 0 */ + Rdt = 0x00002818, /* Receive Descriptor Tail Queue 0 */ + Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */ + Rxdctl = 0x00002828, /* Receive Descriptor Control */ + Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */ + Rdbal1 = 0x00002900, /* Rdesc Base Address Low Queue 1 */ + Rdbah1 = 0x00002804, /* Rdesc Base Address High Queue 1 */ + Rdlen1 = 0x00002908, /* Receive Descriptor Length Queue 1 */ + Rdh1 = 0x00002910, /* Receive Descriptor Head Queue 1 */ + Rdt1 = 0x00002918, /* Receive Descriptor Tail Queue 1 */ + Rxdctl1 = 0x00002928, /* Receive Descriptor Control Queue 1 */ + Rsrpd = 0x00002c00, /* Receive Small Packet Detect */ + Raid = 0x00002c08, /* Receive ACK interrupt delay */ + Cpuvec = 0x00002c10, /* CPU Vector */ + Rxcsum = 0x00005000, /* Receive Checksum Control */ + Rfctl = 0x00005008, /* Receive Filter Control */ + Mta = 0x00005200, /* Multicast Table Array */ + Ral = 0x00005400, /* Receive Address Low */ + Rah = 0x00005404, /* Receive Address High */ + Vfta = 0x00005600, /* VLAN Filter Table Array */ + Mrqc = 0x00005818, /* Multiple Receive Queues Command */ + Rssim = 0x00005864, /* RSS Interrupt Mask */ + Rssir = 0x00005868, /* RSS Interrupt Request */ + Reta = 0x00005c00, /* Redirection Table */ + Rssrk = 0x00005c80, /* RSS Random Key */ + + /* Transmit */ + + Tctl = 0x00000400, /* Transmit Control */ + Tipg = 0x00000410, /* Transmit IPG */ + Tdbal = 0x00003800, /* Tdesc Base Address Low */ + Tdbah = 0x00003804, /* Tdesc Base Address High */ + Tdlen = 0x00003808, /* Transmit Descriptor Length */ + Tdh = 0x00003810, /* Transmit Descriptor Head */ + Tdt = 0x00003818, /* Transmit Descriptor Tail */ + Tidv = 0x00003820, /* Transmit Interrupt Delay Value */ + Txdctl = 0x00003828, /* Transmit Descriptor Control */ + Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */ + Tarc0 = 0x00003840, /* Transmit Arbitration Counter Queue 0 */ + Tdbal1 = 0x00003900, /* Transmit Descriptor Base Low Queue 1 */ + Tdbah1 = 0x00003904, /* Transmit Descriptor Base High Queue 1 */ + Tdlen1 = 0x00003908, /* Transmit Descriptor Length Queue 1 */ + Tdh1 = 0x00003910, /* Transmit Descriptor Head Queue 1 */ + Tdt1 = 0x00003918, /* Transmit Descriptor Tail Queue 1 */ + Txdctl1 = 0x00003928, /* Transmit Descriptor Control 1 */ + Tarc1 = 0x00003940, /* Transmit Arbitration Counter Queue 1 */ + + /* Statistics */ + + Statistics = 0x00004000, /* Start of Statistics Area */ + Gorcl = 0x88/4, /* Good Octets Received Count */ + Gotcl = 0x90/4, /* Good Octets Transmitted Count */ + Torl = 0xC0/4, /* Total Octets Received */ + Totl = 0xC8/4, /* Total Octets Transmitted */ + Nstatistics = 64, + +}; + +enum { /* Ctrl */ + GIOmd = 1<<2, /* BIO master disable */ + Lrst = 1<<3, /* link reset */ + Slu = 1<<6, /* Set Link Up */ + SspeedMASK = 3<<8, /* Speed Selection */ + SspeedSHIFT = 8, + Sspeed10 = 0x00000000, /* 10Mb/s */ + Sspeed100 = 0x00000100, /* 100Mb/s */ + Sspeed1000 = 0x00000200, /* 1000Mb/s */ + Frcspd = 1<<11, /* Force Speed */ + Frcdplx = 1<<12, /* Force Duplex */ + SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */ + SwdpinsloSHIFT = 18, + SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */ + SwdpioloSHIFT = 22, + Devrst = 1<<26, /* Device Reset */ + Rfce = 1<<27, /* Receive Flow Control Enable */ + Tfce = 1<<28, /* Transmit Flow Control Enable */ + Vme = 1<<30, /* VLAN Mode Enable */ + Phy_rst = 1<<31, /* Phy Reset */ +}; + +enum { /* Status */ + Lu = 1<<1, /* Link Up */ + Lanid = 3<<2, /* mask for Lan ID. */ + Txoff = 1<<4, /* Transmission Paused */ + Tbimode = 1<<5, /* TBI Mode Indication */ + SpeedMASK = 0x000000C0, + Speed10 = 0x00000000, /* 10Mb/s */ + Speed100 = 0x00000040, /* 100Mb/s */ + Speed1000 = 0x00000080, /* 1000Mb/s */ + Phyra = 1<<10, /* PHY Reset Asserted */ + GIOme = 1<<19, /* GIO Master Enable Status */ +}; + +enum { /* Ctrl and Status */ + Fd = 0x00000001, /* Full-Duplex */ + AsdvMASK = 0x00000300, + Asdv10 = 0x00000000, /* 10Mb/s */ + Asdv100 = 0x00000100, /* 100Mb/s */ + Asdv1000 = 0x00000200, /* 1000Mb/s */ +}; + +enum { /* Eec */ + Sk = 1<<0, /* Clock input to the EEPROM */ + Cs = 1<<1, /* Chip Select */ + Di = 1<<2, /* Data Input to the EEPROM */ + Do = 1<<3, /* Data Output from the EEPROM */ + Areq = 1<<6, /* EEPROM Access Request */ + Agnt = 1<<7, /* EEPROM Access Grant */ +}; + +enum { /* Eerd */ + ee_start = 1<<0, /* Start Read */ + ee_done = 1<<1, /* Read done */ + ee_addr = 0xfff8<<2, /* Read address [15:2] */ + ee_data = 0xffff<<16, /* Read Data; Data returned from eeprom/nvm */ +}; + +enum { /* Ctrlext */ + Asdchk = 1<<12, /* ASD Check */ + Eerst = 1<<13, /* EEPROM Reset */ + Spdbyps = 1<<15, /* Speed Select Bypass */ +}; + +enum { /* EEPROM content offsets */ + Ea = 0x00, /* Ethernet Address */ + Cf = 0x03, /* Compatibility Field */ + Icw1 = 0x0A, /* Initialization Control Word 1 */ + Sid = 0x0B, /* Subsystem ID */ + Svid = 0x0C, /* Subsystem Vendor ID */ + Did = 0x0D, /* Device ID */ + Vid = 0x0E, /* Vendor ID */ + Icw2 = 0x0F, /* Initialization Control Word 2 */ +}; + +enum { /* Mdic */ + MDIdMASK = 0x0000FFFF, /* Data */ + MDIdSHIFT = 0, + MDIrMASK = 0x001F0000, /* PHY Register Address */ + MDIrSHIFT = 16, + MDIpMASK = 0x03E00000, /* PHY Address */ + MDIpSHIFT = 21, + MDIwop = 0x04000000, /* Write Operation */ + MDIrop = 0x08000000, /* Read Operation */ + MDIready = 0x10000000, /* End of Transaction */ + MDIie = 0x20000000, /* Interrupt Enable */ + MDIe = 0x40000000, /* Error */ +}; + +enum { /* Icr, Ics, Ims, Imc */ + Txdw = 0x00000001, /* Transmit Descriptor Written Back */ + Txqe = 0x00000002, /* Transmit Queue Empty */ + Lsc = 0x00000004, /* Link Status Change */ + Rxseq = 0x00000008, /* Receive Sequence Error */ + Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */ + Rxo = 0x00000040, /* Receiver Overrun */ + Rxt0 = 0x00000080, /* Receiver Timer Interrupt */ + Mdac = 0x00000200, /* MDIO Access Completed */ + Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */ + Gpi0 = 0x00000800, /* General Purpose Interrupts */ + Gpi1 = 0x00001000, + Gpi2 = 0x00002000, + Gpi3 = 0x00004000, + Ack = 0x00020000, /* receive ACK frame */ +}; + +enum { /* Txcw */ + TxcwFd = 0x00000020, /* Full Duplex */ + TxcwHd = 0x00000040, /* Half Duplex */ + TxcwPauseMASK = 0x00000180, /* Pause */ + TxcwPauseSHIFT = 7, + TxcwPs = 1<<TxcwPauseSHIFT, /* Pause Supported */ + TxcwAs = 2<<TxcwPauseSHIFT, /* Asymmetric FC desired */ + TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */ + TxcwRfiSHIFT = 12, + TxcwNpr = 0x00008000, /* Next Page Request */ + TxcwConfig = 0x40000000, /* Transmit COnfig Control */ + TxcwAne = 0x80000000, /* Auto-Negotiation Enable */ +}; + +enum { /* Rctl */ + Rrst = 0x00000001, /* Receiver Software Reset */ + Ren = 0x00000002, /* Receiver Enable */ + Sbp = 0x00000004, /* Store Bad Packets */ + Upe = 0x00000008, /* Unicast Promiscuous Enable */ + Mpe = 0x00000010, /* Multicast Promiscuous Enable */ + Lpe = 0x00000020, /* Long Packet Reception Enable */ + LbmMASK = 0x000000C0, /* Loopback Mode */ + LbmOFF = 0x00000000, /* No Loopback */ + LbmTBI = 0x00000040, /* TBI Loopback */ + LbmMII = 0x00000080, /* GMII/MII Loopback */ + LbmXCVR = 0x000000C0, /* Transceiver Loopback */ + RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */ + RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */ + RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */ + RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */ + MoMASK = 0x00003000, /* Multicast Offset */ + Bam = 0x00008000, /* Broadcast Accept Mode */ + BsizeMASK = 0x00030000, /* Receive Buffer Size */ + Bsize2048 = 0x00000000, + Bsize1024 = 0x00010000, + Bsize512 = 0x00020000, + Bsize256 = 0x00030000, + Vfe = 0x00040000, /* VLAN Filter Enable */ + Cfien = 0x00080000, /* Canonical Form Indicator Enable */ + Cfi = 0x00100000, /* Canonical Form Indicator value */ + Dpf = 0x00400000, /* Discard Pause Frames */ + Pmcf = 0x00800000, /* Pass MAC Control Frames */ + Bsex = 0x02000000, /* Buffer Size Extension */ + Secrc = 0x04000000, /* Strip CRC from incoming packet */ +}; + +enum { /* Tctl */ + Trst = 0x00000001, /* Transmitter Software Reset */ + Ten = 0x00000002, /* Transmit Enable */ + Psp = 0x00000008, /* Pad Short Packets */ + Mulr = 0x10000000, /* Allow multiple concurrent requests */ + CtMASK = 0x00000FF0, /* Collision Threshold */ + CtSHIFT = 4, + ColdMASK = 0x003FF000, /* Collision Distance */ + ColdSHIFT = 12, + Swxoff = 0x00400000, /* Sofware XOFF Transmission */ + Pbe = 0x00800000, /* Packet Burst Enable */ + Rtlc = 0x01000000, /* Re-transmit on Late Collision */ + Nrtu = 0x02000000, /* No Re-transmit on Underrrun */ +}; + +enum { /* [RT]xdctl */ + PthreshMASK = 0x0000003F, /* Prefetch Threshold */ + PthreshSHIFT = 0, + HthreshMASK = 0x00003F00, /* Host Threshold */ + HthreshSHIFT = 8, + WthreshMASK = 0x003F0000, /* Writebacj Threshold */ + WthreshSHIFT = 16, + Gran = 0x01000000, /* Granularity */ +}; + +enum { /* Rxcsum */ + PcssMASK = 0x000000FF, /* Packet Checksum Start */ + PcssSHIFT = 0, + Ipofl = 0x00000100, /* IP Checksum Off-load Enable */ + Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */ +}; + +typedef struct Rdesc { /* Receive Descriptor */ + uint addr[2]; + ushort length; + ushort checksum; + uchar status; + uchar errors; + ushort special; +} Rdesc; + +enum { /* Rdesc status */ + Rdd = 0x01, /* Descriptor Done */ + Reop = 0x02, /* End of Packet */ + Ixsm = 0x04, /* Ignore Checksum Indication */ + Vp = 0x08, /* Packet is 802.1Q (matched VET) */ + Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */ + Ipcs = 0x40, /* IP Checksum Calculated on Packet */ + Pif = 0x80, /* Passed in-exact filter */ +}; + +enum { /* Rdesc errors */ + Ce = 0x01, /* CRC Error or Alignment Error */ + Se = 0x02, /* Symbol Error */ + Seq = 0x04, /* Sequence Error */ + Cxe = 0x10, /* Carrier Extension Error */ + Tcpe = 0x20, /* TCP/UDP Checksum Error */ + Ipe = 0x40, /* IP Checksum Error */ + Rxe = 0x80, /* RX Data Error */ +}; + +typedef struct Tdesc { /* Legacy+Normal Transmit Descriptor */ + uint addr[2]; + uint control; /* varies with descriptor type */ + uint status; /* varies with descriptor type */ +} Tdesc; + +enum { /* Tdesc control */ + LenMASK = 0x000FFFFF, /* Data/Packet Length Field */ + LenSHIFT = 0, + DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */ + DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */ + PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */ + Teop = 0x01000000, /* End of Packet (DD) */ + PtypeIP = 0x02000000, /* IP Packet Type (CD) */ + Ifcs = 0x02000000, /* Insert FCS (DD) */ + Tse = 0x04000000, /* TCP Segmentation Enable */ + Rs = 0x08000000, /* Report Status */ + Rps = 0x10000000, /* Report Status Sent */ + Dext = 0x20000000, /* Descriptor Extension */ + Vle = 0x40000000, /* VLAN Packet Enable */ + Ide = 0x80000000, /* Interrupt Delay Enable */ +}; + +enum { /* Tdesc status */ + Tdd = 0x00000001, /* Descriptor Done */ + Ec = 0x00000002, /* Excess Collisions */ + Lc = 0x00000004, /* Late Collision */ + Tu = 0x00000008, /* Transmit Underrun */ + CssMASK = 0x0000FF00, /* Checksum Start Field */ + CssSHIFT = 8, +}; + +enum { + Nrdesc = 128, /* multiple of 8 */ + Ntdesc = 128, /* multiple of 8 */ +}; + +enum { + i82563, + i82571, + i82573, +}; + +static char *tname[] = { + "i82563", + "i82571", + "i82573", +}; + +#define Type tname[ctlr->type] + +typedef struct Ctlr Ctlr; +struct Ctlr { + int port; + Pcidev *pcidev; + Ctlr *next; + int active; + int cls; + ushort eeprom[0x40]; + uchar ra[Eaddrlen]; /* receive address */ + int type; + + int* nic; + Lock imlock; + int im; /* interrupt mask */ + + Lock slock; + uint statistics[Nstatistics]; + + Rdesc *rdba; /* receive descriptor base address */ + Block **rb; /* receive buffers */ + int rdh; /* receive descriptor head */ + int rdt; /* receive descriptor tail */ + + Tdesc *tdba; /* transmit descriptor base address */ + Lock tdlock; + Block **tb; /* transmit buffers */ + int tdh; /* transmit descriptor head */ + int tdt; /* transmit descriptor tail */ + + int txcw; + int fcrtl; + int fcrth; + + /* bootstrap goo */ + Block *bqhead; /* transmission queue */ + Block *bqtail; +}; + +static Ctlr *ctlrhead; +static Ctlr *ctlrtail; + +#define csr32r(c, r) (*((c)->nic+((r)/4))) +#define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v)) + +static void +i82563im(Ctlr* ctlr, int im) +{ + ilock(&ctlr->imlock); + ctlr->im |= im; + csr32w(ctlr, Ims, ctlr->im); + iunlock(&ctlr->imlock); +} + +static void +i82563attach(Ether* edev) +{ + int ctl; + Ctlr *ctlr; + + ctlr = edev->ctlr; + i82563im(ctlr, 0); + ctl = csr32r(ctlr, Rctl)|Ren; + csr32w(ctlr, Rctl, ctl); + ctl = csr32r(ctlr, Tctl)|Ten; + csr32w(ctlr, Tctl, ctl); +} + + +static void +txstart(Ether *edev) +{ + int tdh, tdt; + Ctlr *ctlr = edev->ctlr; + Block *bp; + Tdesc *tdesc; + + /* + * Try to fill the ring back up, moving buffers from the transmit q. + */ + tdh = PREV(ctlr->tdh, Ntdesc); + for(tdt = ctlr->tdt; tdt != tdh; tdt = NEXT(tdt, Ntdesc)){ + /* pull off the head of the transmission queue */ + if((bp = ctlr->bqhead) == nil) /* was qget(edev->oq) */ + break; + ctlr->bqhead = bp->next; + if (ctlr->bqtail == bp) + ctlr->bqtail = nil; + + /* set up a descriptor for it */ + tdesc = &ctlr->tdba[tdt]; + tdesc->addr[0] = PCIWADDR(bp->rp); + tdesc->addr[1] = 0; + tdesc->control = /* Ide | */ Rs | Ifcs | Teop | BLEN(bp); + + ctlr->tb[tdt] = bp; + } + ctlr->tdt = tdt; + csr32w(ctlr, Tdt, tdt); + i82563im(ctlr, Txdw); +} + +static Block * +fromringbuf(Ether *ether) +{ + RingBuf *tb = ðer->tb[ether->ti]; + Block *bp = allocb(tb->len); + + memmove(bp->wp, tb->pkt, tb->len); + memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen); + bp->wp += tb->len; + return bp; +} + +static void +i82563transmit(Ether* edev) +{ + Block *bp; + Ctlr *ctlr; + Tdesc *tdesc; + RingBuf *tb; + int tdh; + + ctlr = edev->ctlr; + ilock(&ctlr->tdlock); + + /* + * Free any completed packets + * - try to get the soft tdh to catch the tdt; + * - if the packet had an underrun bump the threshold + * - the Tu bit doesn't seem to ever be set, perhaps + * because Rs mode is used? + */ + tdh = ctlr->tdh; + for(;;){ + tdesc = &ctlr->tdba[tdh]; + if(!(tdesc->status & Tdd)) + break; + if(ctlr->tb[tdh] != nil){ + freeb(ctlr->tb[tdh]); + ctlr->tb[tdh] = nil; + } + tdesc->status = 0; + tdh = NEXT(tdh, Ntdesc); + } + ctlr->tdh = tdh; + + /* copy packets from the software RingBuf to the transmission q */ + while((tb = &edev->tb[edev->ti])->owner == Interface){ + bp = fromringbuf(edev); +// print("#l%d: tx %d %E %E\n", edev->ctlrno, edev->ti, bp->rp, +// bp->rp+6); + + if(ctlr->bqhead) + ctlr->bqtail->next = bp; + else + ctlr->bqhead = bp; + ctlr->bqtail = bp; + + txstart(edev); /* kick transmitter */ + tb->owner = Host; /* give descriptor back */ + edev->ti = NEXT(edev->ti, edev->ntb); + } + iunlock(&ctlr->tdlock); +} + +static void +i82563replenish(Ctlr* ctlr) +{ + int rdt; + Block *bp; + Rdesc *rdesc; + + rdt = ctlr->rdt; + while(NEXT(rdt, Nrdesc) != ctlr->rdh){ + rdesc = &ctlr->rdba[rdt]; + if(ctlr->rb[rdt] != nil){ + /* nothing to do */ + } + else if((bp = iallocb(2048)) != nil){ + ctlr->rb[rdt] = bp; + rdesc->addr[0] = PCIWADDR(bp->rp); + rdesc->addr[1] = 0; + } + else + break; + rdesc->status = 0; + + rdt = NEXT(rdt, Nrdesc); + } + ctlr->rdt = rdt; + csr32w(ctlr, Rdt, rdt); +} + +static void +toringbuf(Ether *ether, Block *bp) +{ + RingBuf *rb = ðer->rb[ether->ri]; + + if (rb->owner == Interface) { + rb->len = BLEN(bp); + memmove(rb->pkt, bp->rp, rb->len); + rb->owner = Host; + ether->ri = NEXT(ether->ri, ether->nrb); + } else if (debug) + print("#l%d: toringbuf: dropping packets @ ri %d\n", + ether->ctlrno, ether->ri); +} + +static void +i82563interrupt(Ureg*, void* arg) +{ + int icr, im, rdh, txdw = 0; + Block *bp; + Ctlr *ctlr; + Ether *edev; + Rdesc *rdesc; + + edev = arg; + ctlr = edev->ctlr; + + ilock(&ctlr->imlock); + csr32w(ctlr, Imc, ~0); + im = ctlr->im; + + for(icr = csr32r(ctlr, Icr); icr & ctlr->im; icr = csr32r(ctlr, Icr)){ + if(icr & (Rxseq|Lsc)){ + /* should be more here */ + } + + rdh = ctlr->rdh; + for (;;) { + rdesc = &ctlr->rdba[rdh]; + if(!(rdesc->status & Rdd)) + break; + if ((rdesc->status & Reop) && rdesc->errors == 0) { + bp = ctlr->rb[rdh]; + if(0 && memcmp(bp->rp, broadcast, 6) != 0) + print("#l%d: rx %d %E %E %d\n", + edev->ctlrno, rdh, bp->rp, + bp->rp+6, rdesc->length); + ctlr->rb[rdh] = nil; + bp->wp += rdesc->length; + toringbuf(edev, bp); + freeb(bp); + } else if (rdesc->status & Reop && rdesc->errors) + print("%s: input packet error 0x%ux\n", + Type, rdesc->errors); + rdesc->status = 0; + rdh = NEXT(rdh, Nrdesc); + } + ctlr->rdh = rdh; + if(icr & Rxdmt0) + i82563replenish(ctlr); + if(icr & Txdw){ + im &= ~Txdw; + txdw++; + } + } + ctlr->im = im; + csr32w(ctlr, Ims, im); + iunlock(&ctlr->imlock); + if(txdw) + i82563transmit(edev); +} + +static void +i82563init(Ether* edev) +{ + int csr, i, r; + Ctlr *ctlr; + + ctlr = edev->ctlr; + csr = edev->ea[3]<<24 | edev->ea[2]<<16 | edev->ea[1]<<8 | edev->ea[0]; + csr32w(ctlr, Ral, csr); + csr = 0x80000000 | edev->ea[5]<<8 | edev->ea[4]; + csr32w(ctlr, Rah, csr); + for (i = 1; i < 16; i++) { + csr32w(ctlr, Ral+i*8, 0); + csr32w(ctlr, Rah+i*8, 0); + } + for(i = 0; i < 128; i++) + csr32w(ctlr, Mta+i*4, 0); + csr32w(ctlr, Rctl, 0); + ctlr->rdba = xspanalloc(Nrdesc*sizeof(Rdesc), 256, 0); + csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba)); + csr32w(ctlr, Rdbah, 0); + csr32w(ctlr, Rdlen, Nrdesc*sizeof(Rdesc)); + ctlr->rdh = 0; + csr32w(ctlr, Rdh, ctlr->rdh); + ctlr->rdt = 0; + csr32w(ctlr, Rdt, ctlr->rdt); + ctlr->rb = malloc(sizeof(Block*)*Nrdesc); + i82563replenish(ctlr); + csr32w(ctlr, Rdtr, 0); + csr32w(ctlr, Rctl, Dpf | Bsize2048 | Bam | RdtmsHALF); + i82563im(ctlr, Rxt0 | Rxo | Rxdmt0 | Rxseq | Ack); + + csr32w(ctlr, Tctl, 0x0F<<CtSHIFT | Psp | 0x3f<<ColdSHIFT | Mulr); + csr32w(ctlr, Tipg, 6<<20 | 8<<10 | 8); + csr32w(ctlr, Tidv, 1); + + ctlr->tdba = xspanalloc(Ntdesc*sizeof(Tdesc), 256, 0); + memset(ctlr->tdba, 0, Ntdesc*sizeof(Tdesc)); + csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba)); + + csr32w(ctlr, Tdbah, 0); + csr32w(ctlr, Tdlen, Ntdesc*sizeof(Tdesc)); + ctlr->tdh = 0; + csr32w(ctlr, Tdh, ctlr->tdh); + ctlr->tdt = 0; + csr32w(ctlr, Tdt, ctlr->tdt); + ctlr->tb = malloc(sizeof(Block*)*Ntdesc); + +// r = 4<<WthreshSHIFT | 4<<HthreshSHIFT | 8<<PthreshSHIFT; +// csr32w(ctlr, Txdctl, r); + csr32w(ctlr, Rxcsum, Tuofl | Ipofl | ETHERHDRSIZE<<PcssSHIFT); + r = csr32r(ctlr, Tctl); + r |= Ten; + csr32w(ctlr, Tctl, r); +} + + +static ushort +eeread(Ctlr* ctlr, int adr) +{ + csr32w(ctlr, Eerd, ee_start | adr << 2); + while ((csr32r(ctlr, Eerd) & ee_done) == 0) + ; + return csr32r(ctlr, Eerd) >> 16; +} + +static int +eeload(Ctlr* ctlr) +{ + ushort sum; + int data, adr; + + sum = 0; + for (adr = 0; adr < 0x40; adr++) { + data = eeread(ctlr, adr); + ctlr->eeprom[adr] = data; + sum += data; + } + return sum; +} + + +static void +detach(Ctlr *ctlr) +{ + int r; + + csr32w(ctlr, Imc, ~0); + csr32w(ctlr, Rctl, 0); + csr32w(ctlr, Tctl, 0); + + delay(10); + + r = csr32r(ctlr, Ctrl); + csr32w(ctlr, Ctrl, Devrst | r); + /* apparently needed on multi-GHz processors to avoid infinite loops */ + delay(1); + while(csr32r(ctlr, Ctrl) & Devrst) + ; + + if(1 || ctlr->type != i82563){ + r = csr32r(ctlr, Ctrl); + csr32w(ctlr, Ctrl, Slu | r); + } + + csr32w(ctlr, Ctrlext, Eerst | csr32r(ctlr, Ctrlext)); + delay(1); + while(csr32r(ctlr, Ctrlext) & Eerst) + ; + + csr32w(ctlr, Imc, ~0); + delay(1); + while(csr32r(ctlr, Icr)) + ; +} + +static void +i82563detach(Ether *edev) +{ + detach(edev->ctlr); +} + +static void +i82563shutdown(Ether* ether) +{ + i82563detach(ether); +} + +static int +i82563reset(Ctlr* ctlr) +{ + int i, r; + + detach(ctlr); + + r = eeload(ctlr); + if (r != 0 && r != 0xBABA){ + print("%s: bad EEPROM checksum - 0x%4.4ux\n", Type, r); + return -1; + } + + for(i = Ea; i < Eaddrlen/2; i++){ + ctlr->ra[2*i] = ctlr->eeprom[i]; + ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8; + } + r = (csr32r(ctlr, Status) & Lanid) >> 2; + ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */ + + r = ctlr->ra[3]<<24 | ctlr->ra[2]<<16 | ctlr->ra[1]<<8 | ctlr->ra[0]; + csr32w(ctlr, Ral, r); + r = 0x80000000 | ctlr->ra[5]<<8 | ctlr->ra[4]; + csr32w(ctlr, Rah, r); + for(i = 1; i < 16; i++){ + csr32w(ctlr, Ral+i*8, 0); + csr32w(ctlr, Rah+i*8, 0); + } + + for(i = 0; i < 128; i++) + csr32w(ctlr, Mta+i*4, 0); + + csr32w(ctlr, Fcal, 0x00C28001); + csr32w(ctlr, Fcah, 0x00000100); + csr32w(ctlr, Fct, 0x00008808); + csr32w(ctlr, Fcttv, 0x00000100); + + csr32w(ctlr, Fcrtl, ctlr->fcrtl); + csr32w(ctlr, Fcrth, ctlr->fcrth); + + ilock(&ctlr->imlock); + csr32w(ctlr, Imc, ~0); + ctlr->im = 0; /* was = Lsc, which hangs some controllers */ + csr32w(ctlr, Ims, ctlr->im); + iunlock(&ctlr->imlock); + + return 0; +} + +static void +i82563pci(void) +{ + int port, type, cls; + Pcidev *p; + Ctlr *ctlr; + static int first = 1; + + if (first) + first = 0; + else + return; + + p = nil; + while(p = pcimatch(p, 0x8086, 0)){ + switch(p->did){ + case 0x1096: + case 0x10ba: + type = i82563; + break; + case 0x108b: /* e */ + case 0x108c: /* e (iamt) */ + case 0x109a: /* l */ + type = i82573; + break; + default: + continue; + } + + port = upamalloc(p->mem[0].bar & ~0x0F, p->mem[0].size, 0); + if(port == 0){ + print("%s: can't map %d @ 0x%8.8lux\n", tname[type], + p->mem[0].size, p->mem[0].bar); + continue; + } + + if(p->pcr & MemWrInv){ + cls = pcicfgr8(p, PciCLS) * 4; + if(cls != CACHELINESZ) + pcicfgw8(p, PciCLS, CACHELINESZ/4); + } + + cls = pcicfgr8(p, PciCLS); + switch(cls){ + default: + print("%s: unexpected CLS - %d bytes\n", + tname[type], cls*sizeof(long)); + break; + case 0x00: + case 0xFF: + /* alphapc 164lx returns 0 */ + print("%s: unusable PciCLS: %d, using %d longs\n", + tname[type], cls, CACHELINESZ/sizeof(long)); + cls = CACHELINESZ/sizeof(long); + pcicfgw8(p, PciCLS, cls); + break; + case 0x08: + case 0x10: + break; + } + + ctlr = malloc(sizeof(Ctlr)); + ctlr->port = port; + ctlr->pcidev = p; + ctlr->cls = cls*4; + ctlr->type = type; + ctlr->nic = KADDR(ctlr->port); + if(i82563reset(ctlr)){ + free(ctlr); + continue; + } + pcisetbme(p); + + if(ctlrhead != nil) + ctlrtail->next = ctlr; + else + ctlrhead = ctlr; + ctlrtail = ctlr; + } +} + +static uchar nilea[Eaddrlen]; + +int +i82563pnp(Ether* edev) +{ + Ctlr *ctlr; + + if(ctlrhead == nil) + i82563pci(); + + /* + * Any adapter matches if no edev->port is supplied, + * otherwise the ports must match. + */ + for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){ + if(ctlr->active) + continue; + if(edev->port == 0 || edev->port == ctlr->port){ + ctlr->active = 1; + break; + } + } + if(ctlr == nil) + return -1; + + edev->ctlr = ctlr; + edev->port = ctlr->port; + edev->irq = ctlr->pcidev->intl; + edev->tbdf = ctlr->pcidev->tbdf; +// edev->mbps = 1000; + + if(memcmp(edev->ea, nilea, Eaddrlen) == 0) + memmove(edev->ea, ctlr->ra, Eaddrlen); + i82563init(edev); + + /* + * Linkage to the generic ethernet driver. + */ + edev->attach = i82563attach; + edev->transmit = i82563transmit; + edev->interrupt = i82563interrupt; + edev->detach = i82563detach; + + /* + * with the current structure, there is no right place for this. + * ideally, we recognize the interface, note it's down and move on. + * currently either we can skip the interface or note it is down, + * but not both. + */ + if((csr32r(ctlr, Status)&Lu) == 0){ + print("ether#%d: 82563 (%s): link down\n", edev->ctlrno, Type); + return -1; + } + + return 0; +} diff --git a/os/boot/pc/ether83815.c b/os/boot/pc/ether83815.c index 71a1c24d..f386cce7 100644 --- a/os/boot/pc/ether83815.c +++ b/os/boot/pc/ether83815.c @@ -286,11 +286,6 @@ enum { #define csr16w(c, r, l) (outs((c)->port+(r), (ulong)(l))) static void -coherence(void) -{ -} - -static void dumpcregs(Ctlr *ctlr) { int i; diff --git a/os/boot/pc/etherdp83820.c b/os/boot/pc/etherdp83820.c new file mode 100644 index 00000000..a7b2c770 --- /dev/null +++ b/os/boot/pc/etherdp83820.c @@ -0,0 +1,1222 @@ +/* + * boot driver for + * National Semiconductor DP83820 + * 10/100/1000 Mb/s Ethernet Network Interface Controller + * (Gig-NIC). + * Driver assumes little-endian and 32-bit host throughout. + */ +#include "u.h" +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" + +#include "etherif.h" +#include "ethermii.h" + +#define iprint print +#define waserror() (0) +#define poperror() + +enum { /* Registers */ + Cr = 0x00, /* Command */ + Cfg = 0x04, /* Configuration and Media Status */ + Mear = 0x08, /* MII/EEPROM Access */ + Ptscr = 0x0C, /* PCI Test Control */ + Isr = 0x10, /* Interrupt Status */ + Imr = 0x14, /* Interrupt Mask */ + Ier = 0x18, /* Interrupt Enable */ + Ihr = 0x1C, /* Interrupt Holdoff */ + Txdp = 0x20, /* Transmit Descriptor Pointer */ + Txdphi = 0x24, /* Transmit Descriptor Pointer Hi */ + Txcfg = 0x28, /* Transmit Configuration */ + Gpior = 0x2C, /* General Purpose I/O Control */ + Rxdp = 0x30, /* Receive Descriptor Pointer */ + Rxdphi = 0x34, /* Receive Descriptor Pointer Hi */ + Rxcfg = 0x38, /* Receive Configuration */ + Pqcr = 0x3C, /* Priority Queueing Control */ + Wcsr = 0x40, /* Wake on LAN Control/Status */ + Pcr = 0x44, /* Pause Control/Status */ + Rfcr = 0x48, /* Receive Filter/Match Control */ + Rfdr = 0x4C, /* Receive Filter/Match Data */ + Brar = 0x50, /* Boot ROM Address */ + Brdr = 0x54, /* Boot ROM Data */ + Srr = 0x58, /* Silicon Revision */ + Mibc = 0x5C, /* MIB Control */ + Mibd = 0x60, /* MIB Data */ + Txdp1 = 0xA0, /* Txdp Priority 1 */ + Txdp2 = 0xA4, /* Txdp Priority 2 */ + Txdp3 = 0xA8, /* Txdp Priority 3 */ + Rxdp1 = 0xB0, /* Rxdp Priority 1 */ + Rxdp2 = 0xB4, /* Rxdp Priority 2 */ + Rxdp3 = 0xB8, /* Rxdp Priority 3 */ + Vrcr = 0xBC, /* VLAN/IP Receive Control */ + Vtcr = 0xC0, /* VLAN/IP Transmit Control */ + Vdr = 0xC4, /* VLAN Data */ + Ccsr = 0xCC, /* Clockrun Control/Status */ + Tbicr = 0xE0, /* TBI Control */ + Tbisr = 0xE4, /* TBI Status */ + Tanar = 0xE8, /* TBI ANAR */ + Tanlpar = 0xEC, /* TBI ANLPAR */ + Taner = 0xF0, /* TBI ANER */ + Tesr = 0xF4, /* TBI ESR */ +}; + +enum { /* Cr */ + Txe = 0x00000001, /* Transmit Enable */ + Txd = 0x00000002, /* Transmit Disable */ + Rxe = 0x00000004, /* Receiver Enable */ + Rxd = 0x00000008, /* Receiver Disable */ + Txr = 0x00000010, /* Transmitter Reset */ + Rxr = 0x00000020, /* Receiver Reset */ + Swien = 0x00000080, /* Software Interrupt Enable */ + Rst = 0x00000100, /* Reset */ + TxpriSHFT = 9, /* Tx Priority Queue Select */ + TxpriMASK = 0x00001E00, + RxpriSHFT = 13, /* Rx Priority Queue Select */ + RxpriMASK = 0x0001E000, +}; + +enum { /* Configuration and Media Status */ + Bem = 0x00000001, /* Big Endian Mode */ + Ext125 = 0x00000002, /* External 125MHz reference Select */ + Bromdis = 0x00000004, /* Disable Boot ROM interface */ + Pesel = 0x00000008, /* Parity Error Detection Action */ + Exd = 0x00000010, /* Excessive Deferral Abort */ + Pow = 0x00000020, /* Program Out of Window Timer */ + Sb = 0x00000040, /* Single Back-off */ + Reqalg = 0x00000080, /* PCI Bus Request Algorithm */ + Extstsen = 0x00000100, /* Extended Status Enable */ + Phydis = 0x00000200, /* Disable PHY */ + Phyrst = 0x00000400, /* Reset PHY */ + M64addren = 0x00000800, /* Master 64-bit Addressing Enable */ + Data64en = 0x00001000, /* 64-bit Data Enable */ + Pci64det = 0x00002000, /* PCI 64-bit Bus Detected */ + T64addren = 0x00004000, /* Target 64-bit Addressing Enable */ + Mwidis = 0x00008000, /* MWI Disable */ + Mrmdis = 0x00010000, /* MRM Disable */ + Tmrtest = 0x00020000, /* Timer Test Mode */ + Spdstsien = 0x00040000, /* PHY Spdsts Interrupt Enable */ + Lnkstsien = 0x00080000, /* PHY Lnksts Interrupt Enable */ + Dupstsien = 0x00100000, /* PHY Dupsts Interrupt Enable */ + Mode1000 = 0x00400000, /* 1000Mb/s Mode Control */ + Tbien = 0x01000000, /* Ten-Bit Interface Enable */ + Dupsts = 0x10000000, /* Full Duplex Status */ + Spdsts100 = 0x20000000, /* SPEED100 Input Pin Status */ + Spdsts1000 = 0x40000000, /* SPEED1000 Input Pin Status */ + Lnksts = 0x80000000, /* Link Status */ +}; + +enum { /* MII/EEPROM Access */ + Eedi = 0x00000001, /* EEPROM Data In */ + Eedo = 0x00000002, /* EEPROM Data Out */ + Eeclk = 0x00000004, /* EEPROM Serial Clock */ + Eesel = 0x00000008, /* EEPROM Chip Select */ + Mdio = 0x00000010, /* MII Management Data */ + Mddir = 0x00000020, /* MII Management Direction */ + Mdc = 0x00000040, /* MII Management Clock */ +}; + +enum { /* Interrupts */ + Rxok = 0x00000001, /* Rx OK */ + Rxdesc = 0x00000002, /* Rx Descriptor */ + Rxerr = 0x00000004, /* Rx Packet Error */ + Rxearly = 0x00000008, /* Rx Early Threshold */ + Rxidle = 0x00000010, /* Rx Idle */ + Rxorn = 0x00000020, /* Rx Overrun */ + Txok = 0x00000040, /* Tx Packet OK */ + Txdesc = 0x00000080, /* Tx Descriptor */ + Txerr = 0x00000100, /* Tx Packet Error */ + Txidle = 0x00000200, /* Tx Idle */ + Txurn = 0x00000400, /* Tx Underrun */ + Mib = 0x00000800, /* MIB Service */ + Swi = 0x00001000, /* Software Interrupt */ + Pme = 0x00002000, /* Power Management Event */ + Phy = 0x00004000, /* PHY Interrupt */ + Hibint = 0x00008000, /* High Bits Interrupt Set */ + Rxsovr = 0x00010000, /* Rx Status FIFO Overrun */ + Rtabt = 0x00020000, /* Received Target Abort */ + Rmabt = 0x00040000, /* Received Master Abort */ + Sserr = 0x00080000, /* Signalled System Error */ + Dperr = 0x00100000, /* Detected Parity Error */ + Rxrcmp = 0x00200000, /* Receive Reset Complete */ + Txrcmp = 0x00400000, /* Transmit Reset Complete */ + Rxdesc0 = 0x00800000, /* Rx Descriptor for Priority Queue 0 */ + Rxdesc1 = 0x01000000, /* Rx Descriptor for Priority Queue 1 */ + Rxdesc2 = 0x02000000, /* Rx Descriptor for Priority Queue 2 */ + Rxdesc3 = 0x04000000, /* Rx Descriptor for Priority Queue 3 */ + Txdesc0 = 0x08000000, /* Tx Descriptor for Priority Queue 0 */ + Txdesc1 = 0x10000000, /* Tx Descriptor for Priority Queue 1 */ + Txdesc2 = 0x20000000, /* Tx Descriptor for Priority Queue 2 */ + Txdesc3 = 0x40000000, /* Tx Descriptor for Priority Queue 3 */ +}; + +enum { /* Interrupt Enable */ + Ien = 0x00000001, /* Interrupt Enable */ +}; + +enum { /* Interrupt Holdoff */ + IhSHFT = 0, /* Interrupt Holdoff */ + IhMASK = 0x000000FF, + Ihctl = 0x00000100, /* Interrupt Holdoff Control */ +}; + +enum { /* Transmit Configuration */ + TxdrthSHFT = 0, /* Tx Drain Threshold */ + TxdrthMASK = 0x000000FF, + FlthSHFT = 16, /* Tx Fill Threshold */ + FlthMASK = 0x0000FF00, + Brstdis = 0x00080000, /* 1000Mb/s Burst Disable */ + MxdmaSHFT = 20, /* Max Size per Tx DMA Burst */ + MxdmaMASK = 0x00700000, + Ecretryen = 0x00800000, /* Excessive Collision Retry Enable */ + Atp = 0x10000000, /* Automatic Transmit Padding */ + Mlb = 0x20000000, /* MAC Loopback */ + Hbi = 0x40000000, /* Heartbeat Ignore */ + Csi = 0x80000000, /* Carrier Sense Ignore */ +}; + +enum { /* Receive Configuration */ + RxdrthSHFT = 1, /* Rx Drain Threshold */ + RxdrthMASK = 0x0000003E, + Airl = 0x04000000, /* Accept In-Range Length Errored */ + Alp = 0x08000000, /* Accept Long Packets */ + Rxfd = 0x10000000, /* Receive Full Duplex */ + Stripcrc = 0x20000000, /* Strip CRC */ + Arp = 0x40000000, /* Accept Runt Packets */ + Aep = 0x80000000, /* Accept Errored Packets */ +}; + +enum { /* Priority Queueing Control */ + Txpqen = 0x00000001, /* Transmit Priority Queuing Enable */ + Txfairen = 0x00000002, /* Transmit Fairness Enable */ + RxpqenSHFT = 2, /* Receive Priority Queue Enable */ + RxpqenMASK = 0x0000000C, +}; + +enum { /* Pause Control/Status */ + PscntSHFT = 0, /* Pause Counter Value */ + PscntMASK = 0x0000FFFF, + Pstx = 0x00020000, /* Transmit Pause Frame */ + PsffloSHFT = 18, /* Rx Data FIFO Lo Threshold */ + PsffloMASK = 0x000C0000, + PsffhiSHFT = 20, /* Rx Data FIFO Hi Threshold */ + PsffhiMASK = 0x00300000, + PsstloSHFT = 22, /* Rx Stat FIFO Hi Threshold */ + PsstloMASK = 0x00C00000, + PssthiSHFT = 24, /* Rx Stat FIFO Hi Threshold */ + PssthiMASK = 0x03000000, + Psrcvd = 0x08000000, /* Pause Frame Received */ + Psact = 0x10000000, /* Pause Active */ + Psda = 0x20000000, /* Pause on Destination Address */ + Psmcast = 0x40000000, /* Pause on Multicast */ + Psen = 0x80000000, /* Pause Enable */ +}; + +enum { /* Receive Filter/Match Control */ + RfaddrSHFT = 0, /* Extended Register Address */ + RfaddrMASK = 0x000003FF, + Ulm = 0x00080000, /* U/L bit mask */ + Uhen = 0x00100000, /* Unicast Hash Enable */ + Mhen = 0x00200000, /* Multicast Hash Enable */ + Aarp = 0x00400000, /* Accept ARP Packets */ + ApatSHFT = 23, /* Accept on Pattern Match */ + ApatMASK = 0x07800000, + Apm = 0x08000000, /* Accept on Perfect Match */ + Aau = 0x10000000, /* Accept All Unicast */ + Aam = 0x20000000, /* Accept All Multicast */ + Aab = 0x40000000, /* Accept All Broadcast */ + Rfen = 0x80000000, /* Rx Filter Enable */ +}; + +enum { /* Receive Filter/Match Data */ + RfdataSHFT = 0, /* Receive Filter Data */ + RfdataMASK = 0x0000FFFF, + BmaskSHFT = 16, /* Byte Mask */ + BmaskMASK = 0x00030000, +}; + +enum { /* MIB Control */ + Wrn = 0x00000001, /* Warning Test Indicator */ + Frz = 0x00000002, /* Freeze All Counters */ + Aclr = 0x00000004, /* Clear All Counters */ + Mibs = 0x00000008, /* MIB Counter Strobe */ +}; + +enum { /* MIB Data */ + Nmibd = 11, /* Number of MIB Data Registers */ +}; + +enum { /* VLAN/IP Receive Control */ + Vtden = 0x00000001, /* VLAN Tag Detection Enable */ + Vtren = 0x00000002, /* VLAN Tag Removal Enable */ + Dvtf = 0x00000004, /* Discard VLAN Tagged Frames */ + Dutf = 0x00000008, /* Discard Untagged Frames */ + Ipen = 0x00000010, /* IP Checksum Enable */ + Ripe = 0x00000020, /* Reject IP Checksum Errors */ + Rtcpe = 0x00000040, /* Reject TCP Checksum Errors */ + Rudpe = 0x00000080, /* Reject UDP Checksum Errors */ +}; + +enum { /* VLAN/IP Transmit Control */ + Vgti = 0x00000001, /* VLAN Global Tag Insertion */ + Vppti = 0x00000002, /* VLAN Per-Packet Tag Insertion */ + Gchk = 0x00000004, /* Global Checksum Generation */ + Ppchk = 0x00000008, /* Per-Packet Checksum Generation */ +}; + +enum { /* VLAN Data */ + VtypeSHFT = 0, /* VLAN Type Field */ + VtypeMASK = 0x0000FFFF, + VtciSHFT = 16, /* VLAN Tag Control Information */ + VtciMASK = 0xFFFF0000, +}; + +enum { /* Clockrun Control/Status */ + Clkrunen = 0x00000001, /* CLKRUN Enable */ + Pmeen = 0x00000100, /* PME Enable */ + Pmests = 0x00008000, /* PME Status */ +}; + +typedef struct { + u32int link; /* Link to the next descriptor */ + u32int bufptr; /* pointer to data Buffer */ + int cmdsts; /* Command/Status */ + int extsts; /* optional Extended Status */ + + Block* bp; /* Block containing bufptr */ + u32int unused; /* pad to 64-bit */ +} Desc; + +enum { /* Common cmdsts bits */ + SizeMASK = 0x0000FFFF, /* Descriptor Byte Count */ + SizeSHFT = 0, + Ok = 0x08000000, /* Packet OK */ + Crc = 0x10000000, /* Suppress/Include CRC */ + Intr = 0x20000000, /* Interrupt on ownership transfer */ + More = 0x40000000, /* not last descriptor in a packet */ + Own = 0x80000000, /* Descriptor Ownership */ +}; + +enum { /* Transmit cmdsts bits */ + CcntMASK = 0x000F0000, /* Collision Count */ + CcntSHFT = 16, + Ec = 0x00100000, /* Excessive Collisions */ + Owc = 0x00200000, /* Out of Window Collision */ + Ed = 0x00400000, /* Excessive Deferral */ + Td = 0x00800000, /* Transmit Deferred */ + Crs = 0x01000000, /* Carrier Sense Lost */ + Tfu = 0x02000000, /* Transmit FIFO Underrun */ + Txa = 0x04000000, /* Transmit Abort */ +}; + +enum { /* Receive cmdsts bits */ + Irl = 0x00010000, /* In-Range Length Error */ + Lbp = 0x00020000, /* Loopback Packet */ + Fae = 0x00040000, /* Frame Alignment Error */ + Crce = 0x00080000, /* CRC Error */ + Ise = 0x00100000, /* Invalid Symbol Error */ + Runt = 0x00200000, /* Runt Packet Received */ + Long = 0x00400000, /* Too Long Packet Received */ + DestMASK = 0x01800000, /* Destination Class */ + DestSHFT = 23, + Rxo = 0x02000000, /* Receive Overrun */ + Rxa = 0x04000000, /* Receive Aborted */ +}; + +enum { /* extsts bits */ + EvtciMASK = 0x0000FFFF, /* VLAN Tag Control Information */ + EvtciSHFT = 0, + Vpkt = 0x00010000, /* VLAN Packet */ + Ippkt = 0x00020000, /* IP Packet */ + Iperr = 0x00040000, /* IP Checksum Error */ + Tcppkt = 0x00080000, /* TCP Packet */ + Tcperr = 0x00100000, /* TCP Checksum Error */ + Udppkt = 0x00200000, /* UDP Packet */ + Udperr = 0x00400000, /* UDP Checksum Error */ +}; + +enum { + Nrd = 32, /* was 256 */ + Nrbf = 4*Nrd, + Rbsz = ROUNDUP(sizeof(Etherpkt)+8, 8), + Ntd = 8, /* was 128 */ +}; + +typedef struct Ctlr Ctlr; +struct Ctlr { + int port; + Pcidev* pcidev; + Ctlr* next; + int active; + int id; + + int eepromsz; /* address size in bits */ + ushort* eeprom; + + int* nic; + int cfg; + int imr; + + Lock alock; /* attach */ + Lock ilock; /* init */ + void* alloc; /* base of per-Ctlr allocated data */ + + Mii* mii; + + Lock rdlock; /* receive */ + Desc* rd; + int nrd; + int nrb; + int rdx; + int rxcfg; + + Lock tlock; /* transmit */ + Desc* td; + int ntd; + int tdh; + int tdt; + int ntq; + int txcfg; + + int rxidle; + + uint mibd[Nmibd]; + + int ec; + int owc; + int ed; + int crs; + int tfu; + int txa; +}; + +#define csr32r(c, r) (*((c)->nic+((r)/4))) +#define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v)) + +static Ctlr* dp83820ctlrhead; +static Ctlr* dp83820ctlrtail; + +static Lock dp83820rblock; /* free receive Blocks */ +static Block* dp83820rbpool; + +static char* dp83820mibs[Nmibd] = { + "RXErroredPkts", + "RXFCSErrors", + "RXMsdPktErrors", + "RXFAErrors", + "RXSymbolErrors", + "RXFrameToLong", + "RXIRLErrors", + "RXBadOpcodes", + "RXPauseFrames", + "TXPauseFrames", + "TXSQEErrors", +}; + +static int +mdior(Ctlr* ctlr, int n) +{ + int data, i, mear, r; + + mear = csr32r(ctlr, Mear); + r = ~(Mdc|Mddir) & mear; + data = 0; + for(i = n-1; i >= 0; i--){ + if(csr32r(ctlr, Mear) & Mdio) + data |= (1<<i); + csr32w(ctlr, Mear, Mdc|r); + csr32w(ctlr, Mear, r); + } + csr32w(ctlr, Mear, mear); + + return data; +} + +static void +mdiow(Ctlr* ctlr, int bits, int n) +{ + int i, mear, r; + + mear = csr32r(ctlr, Mear); + r = Mddir|(~Mdc & mear); + for(i = n-1; i >= 0; i--){ + if(bits & (1<<i)) + r |= Mdio; + else + r &= ~Mdio; + csr32w(ctlr, Mear, r); + csr32w(ctlr, Mear, Mdc|r); + } + csr32w(ctlr, Mear, mear); +} + +static int +dp83820miimir(Mii* mii, int pa, int ra) +{ + int data; + Ctlr *ctlr; + + ctlr = mii->ctlr; + + /* + * MII Management Interface Read. + * + * Preamble; + * ST+OP+PA+RA; + * LT + 16 data bits. + */ + mdiow(ctlr, 0xFFFFFFFF, 32); + mdiow(ctlr, 0x1800|(pa<<5)|ra, 14); + data = mdior(ctlr, 18); + + if(data & 0x10000) + return -1; + + return data & 0xFFFF; +} + +static int +dp83820miimiw(Mii* mii, int pa, int ra, int data) +{ + Ctlr *ctlr; + + ctlr = mii->ctlr; + + /* + * MII Management Interface Write. + * + * Preamble; + * ST+OP+PA+RA+LT + 16 data bits; + * Z. + */ + mdiow(ctlr, 0xFFFFFFFF, 32); + data &= 0xFFFF; + data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16); + mdiow(ctlr, data, 32); + + return 0; +} + +static Block * +dp83820rballoc(Desc* desc) +{ + Block *bp; + + if(desc->bp == nil){ + ilock(&dp83820rblock); + if((bp = dp83820rbpool) == nil){ + iunlock(&dp83820rblock); + desc->bp = nil; + desc->cmdsts = Own; + return nil; + } + dp83820rbpool = bp->next; + bp->next = nil; + iunlock(&dp83820rblock); + + desc->bufptr = PCIWADDR(bp->rp); + desc->bp = bp; + } + else{ + bp = desc->bp; + bp->rp = bp->lim - Rbsz; + bp->wp = bp->rp; + } + + coherence(); + desc->cmdsts = Intr|Rbsz; + + return bp; +} + +static void +dp83820rbfree(Block *bp) +{ + bp->rp = bp->lim - Rbsz; + bp->wp = bp->rp; + + ilock(&dp83820rblock); + bp->next = dp83820rbpool; + dp83820rbpool = bp; + iunlock(&dp83820rblock); +} + +static void +dp83820halt(Ctlr* ctlr) +{ + int i, timeo; + + ilock(&ctlr->ilock); + csr32w(ctlr, Imr, 0); + csr32w(ctlr, Ier, 0); + csr32w(ctlr, Cr, Rxd|Txd); + for(timeo = 0; timeo < 1000; timeo++){ + if(!(csr32r(ctlr, Cr) & (Rxe|Txe))) + break; + microdelay(1); + } + csr32w(ctlr, Mibc, Frz); + iunlock(&ctlr->ilock); + + if(ctlr->rd != nil){ + for(i = 0; i < ctlr->nrd; i++){ + if(ctlr->rd[i].bp == nil) + continue; + freeb(ctlr->rd[i].bp); + ctlr->rd[i].bp = nil; + } + } + if(ctlr->td != nil){ + for(i = 0; i < ctlr->ntd; i++){ + if(ctlr->td[i].bp == nil) + continue; + freeb(ctlr->td[i].bp); + ctlr->td[i].bp = nil; + } + } +} + +static void +dp83820cfg(Ctlr* ctlr) +{ + int cfg; + + /* + * Don't know how to deal with a TBI yet. + */ + if(ctlr->mii == nil) + return; + + /* + * The polarity of these bits is at the mercy + * of the board designer. + * The correct answer for all speed and duplex questions + * should be to query the phy. + */ + cfg = csr32r(ctlr, Cfg); + if(!(cfg & Dupsts)){ + ctlr->rxcfg |= Rxfd; + ctlr->txcfg |= Csi|Hbi; + iprint("83820: full duplex, "); + } + else{ + ctlr->rxcfg &= ~Rxfd; + ctlr->txcfg &= ~(Csi|Hbi); + iprint("83820: half duplex, "); + } + csr32w(ctlr, Rxcfg, ctlr->rxcfg); + csr32w(ctlr, Txcfg, ctlr->txcfg); + + switch(cfg & (Spdsts1000|Spdsts100)){ + case Spdsts1000: /* 100Mbps */ + default: /* 10Mbps */ + ctlr->cfg &= ~Mode1000; + if((cfg & (Spdsts1000|Spdsts100)) == Spdsts1000) + iprint("100Mb/s\n"); + else + iprint("10Mb/s\n"); + break; + case Spdsts100: /* 1Gbps */ + ctlr->cfg |= Mode1000; + iprint("1Gb/s\n"); + break; + } + csr32w(ctlr, Cfg, ctlr->cfg); +} + +static void +dp83820init(Ether* edev) +{ + int i; + Ctlr *ctlr; + Desc *desc; + uchar *alloc; + + ctlr = edev->ctlr; + + dp83820halt(ctlr); + + /* + * Receiver + */ + alloc = (uchar*)ROUNDUP((ulong)ctlr->alloc, 8); + ctlr->rd = (Desc*)alloc; + alloc += ctlr->nrd*sizeof(Desc); + memset(ctlr->rd, 0, ctlr->nrd*sizeof(Desc)); + ctlr->rdx = 0; + for(i = 0; i < ctlr->nrd; i++){ + desc = &ctlr->rd[i]; + desc->link = PCIWADDR(&ctlr->rd[NEXT(i, ctlr->nrd)]); + if(dp83820rballoc(desc) == nil) + continue; + } + csr32w(ctlr, Rxdphi, 0); + csr32w(ctlr, Rxdp, PCIWADDR(ctlr->rd)); + + for(i = 0; i < Eaddrlen; i += 2){ + csr32w(ctlr, Rfcr, i); + csr32w(ctlr, Rfdr, (edev->ea[i+1]<<8)|edev->ea[i]); + } + csr32w(ctlr, Rfcr, Rfen|Aab|Aam|Apm); + + ctlr->rxcfg = Stripcrc|(((2*(ETHERMINTU+4))/8)<<RxdrthSHFT); + ctlr->imr |= Rxorn|Rxidle|Rxearly|Rxdesc|Rxok; + + /* + * Transmitter. + */ + ctlr->td = (Desc*)alloc; + memset(ctlr->td, 0, ctlr->ntd*sizeof(Desc)); + ctlr->tdh = ctlr->tdt = ctlr->ntq = 0; + for(i = 0; i < ctlr->ntd; i++){ + desc = &ctlr->td[i]; + desc->link = PCIWADDR(&ctlr->td[NEXT(i, ctlr->ntd)]); + } + csr32w(ctlr, Txdphi, 0); + csr32w(ctlr, Txdp, PCIWADDR(ctlr->td)); + + ctlr->txcfg = Atp|(((2*(ETHERMINTU+4))/32)<<FlthSHFT)|((4096/32)<<TxdrthSHFT); + ctlr->imr |= Txurn|Txidle|Txdesc|Txok; + + ilock(&ctlr->ilock); + + dp83820cfg(ctlr); + + csr32w(ctlr, Mibc, Aclr); + ctlr->imr |= Mib; + + csr32w(ctlr, Imr, ctlr->imr); + + /* try coalescing adjacent interrupts; use hold-off interval of 100µs */ + csr32w(ctlr, Ihr, Ihctl|(1<<IhSHFT)); + + csr32w(ctlr, Ier, Ien); + csr32w(ctlr, Cr, Rxe|Txe); + + iunlock(&ctlr->ilock); +} + +static void +dp83820attach(Ether* edev) +{ + Block *bp; + Ctlr *ctlr; + + ctlr = edev->ctlr; + lock(&ctlr->alock); + if(ctlr->alloc != nil){ + unlock(&ctlr->alock); + return; + } + + if(waserror()){ +err: + if(ctlr->mii != nil){ + free(ctlr->mii); + ctlr->mii = nil; + } + if(ctlr->alloc != nil){ + free(ctlr->alloc); + ctlr->alloc = nil; + } + unlock(&ctlr->alock); + return; + } + + if(!(ctlr->cfg & Tbien)){ + if((ctlr->mii = malloc(sizeof(Mii))) == nil) + goto err; + ctlr->mii->ctlr = ctlr; + ctlr->mii->mir = dp83820miimir; + ctlr->mii->miw = dp83820miimiw; + if(mii(ctlr->mii, ~0) == 0) + goto err; + ctlr->cfg |= Dupstsien|Lnkstsien|Spdstsien; + ctlr->imr |= Phy; + } + + ctlr->nrd = Nrd; + ctlr->nrb = Nrbf; + ctlr->ntd = Ntd; + ctlr->alloc = mallocz((ctlr->nrd+ctlr->ntd)*sizeof(Desc) + 7, 0); + if(ctlr->alloc == nil) + goto err; + + /* + * the Bill Paul bsd drivers claim that receive buffers must be aligned + * on 8-byte boundaries. + */ + for(ctlr->nrb = 0; ctlr->nrb < Nrbf; ctlr->nrb++){ + if((bp = allocb(Rbsz+8-1)) == nil) + break; + bp->rp += 8 - (uintptr)bp->rp % 8; + bp->wp = bp->rp; +// bp->free = dp83820rbfree; /* TODO: fix */ + dp83820rbfree(bp); + } + + dp83820init(edev); + + unlock(&ctlr->alock); + poperror(); +} + +/* + * free a list of blocks + */ +static void +freeblist(Block *b) +{ + Block *next; + + for(; b != 0; b = next){ + next = b->next; + b->next = 0; + freeb(b); + } +} + +static void +toringbuf(Ether *ether, Block *bp) +{ + RingBuf *rb = ðer->rb[ether->ri]; + + if (rb->owner == Interface) { + rb->len = BLEN(bp); + memmove(rb->pkt, bp->rp, rb->len); + rb->owner = Host; + ether->ri = NEXT(ether->ri, ether->nrb); + } + /* else no one is expecting packets from the network */ +} + +static Block * +fromringbuf(Ether *ether) +{ + RingBuf *tb = ðer->tb[ether->ti]; + Block *bp = allocb(tb->len); + + memmove(bp->wp, tb->pkt, tb->len); + memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen); + bp->wp += tb->len; + return bp; +} + +static void +dp83820transmit(Ether* edev) +{ + Block *bp; + Ctlr *ctlr; + Desc *desc; + RingBuf *tb; + int cmdsts, r, x; + + ctlr = edev->ctlr; + + ilock(&ctlr->tlock); + + bp = nil; + for(x = ctlr->tdh; ctlr->ntq; x = NEXT(x, ctlr->ntd)){ + desc = &ctlr->td[x]; + if((cmdsts = desc->cmdsts) & Own) + break; + if(!(cmdsts & Ok)){ + if(cmdsts & Ec) + ctlr->ec++; + if(cmdsts & Owc) + ctlr->owc++; + if(cmdsts & Ed) + ctlr->ed++; + if(cmdsts & Crs) + ctlr->crs++; + if(cmdsts & Tfu) + ctlr->tfu++; + if(cmdsts & Txa) + ctlr->txa++; + } + desc->bp->next = bp; + bp = desc->bp; + desc->bp = nil; + + ctlr->ntq--; + } + ctlr->tdh = x; + if(bp != nil) + freeblist(bp); + + x = ctlr->tdt; +// tb = &edev->tb[edev->ti]; + while(ctlr->ntq < ctlr->ntd - 1 /* && tb->owner == Interface */ ){ + bp = fromringbuf(edev); + if (bp == nil) + break; + + /* transmit packet from bp */ + desc = &ctlr->td[x]; + desc->bufptr = PCIWADDR(bp->rp); + desc->bp = bp; + ctlr->ntq++; + coherence(); + desc->cmdsts = Own|Intr|BLEN(bp); /* kick transmitter */ +//print("t"); + tb = &edev->tb[edev->ti]; + tb->owner = Host; /* give descriptor back */ + edev->ti = NEXT(edev->ti, edev->ntb); + + x = NEXT(x, ctlr->ntd); + } + if(x != ctlr->tdt){ + ctlr->tdt = x; + r = csr32r(ctlr, Cr); + csr32w(ctlr, Cr, Txe|r); + } + + iunlock(&ctlr->tlock); +} + +static void +dp83820interrupt(Ureg*, void* arg) +{ + Block *bp; + Ctlr *ctlr; + Desc *desc; + Ether *edev; + int cmdsts, i, isr, r, x; + + edev = arg; + ctlr = edev->ctlr; + + for(isr = csr32r(ctlr, Isr); isr & ctlr->imr; isr = csr32r(ctlr, Isr)){ + if(isr & (Rxorn|Rxidle|Rxearly|Rxerr|Rxdesc|Rxok)){ + x = ctlr->rdx; + desc = &ctlr->rd[x]; + while((cmdsts = desc->cmdsts) & Own){ + if((cmdsts & Ok) && desc->bp != nil){ + /* receive a packet into desc->bp */ + bp = desc->bp; + desc->bp = nil; + // bp->rp = desc->bufptr; + bp->wp += cmdsts & SizeMASK; + + toringbuf(edev, bp); +//print("r"); + } + dp83820rballoc(desc); + + x = NEXT(x, ctlr->nrd); + desc = &ctlr->rd[x]; + } + ctlr->rdx = x; + + if(isr & Rxidle){ + r = csr32r(ctlr, Cr); + csr32w(ctlr, Cr, Rxe|r); + ctlr->rxidle++; + } + + isr &= ~(Rxorn|Rxidle|Rxearly|Rxerr|Rxdesc|Rxok); + } + + if(isr & Txurn){ + x = (ctlr->txcfg & TxdrthMASK)>>TxdrthSHFT; + r = (ctlr->txcfg & FlthMASK)>>FlthSHFT; + if(x < ((TxdrthMASK)>>TxdrthSHFT) + && x < (2048/32 - r)){ + ctlr->txcfg &= ~TxdrthMASK; + x++; + ctlr->txcfg |= x<<TxdrthSHFT; + csr32w(ctlr, Txcfg, ctlr->txcfg); + } + } + + if(isr & (Txurn|Txidle|Txdesc|Txok)){ + dp83820transmit(edev); + isr &= ~(Txurn|Txidle|Txdesc|Txok); + } + + if(isr & Mib){ + for(i = 0; i < Nmibd; i++){ + r = csr32r(ctlr, Mibd+(i*sizeof(int))); + ctlr->mibd[i] += r & 0xFFFF; + } + isr &= ~Mib; + } + + if((isr & Phy) && ctlr->mii != nil){ + ctlr->mii->mir(ctlr->mii, 1, Bmsr); + print("phy: cfg %8.8uX bmsr %4.4uX\n", + csr32r(ctlr, Cfg), + ctlr->mii->mir(ctlr->mii, 1, Bmsr)); + dp83820cfg(ctlr); + isr &= ~Phy; + } +// TODO fix if(isr) +// TODO fix iprint("dp83820: isr %8.8uX\n", isr); + USED(isr); + } +} + +static int +dp83820detach(Ctlr* ctlr) +{ + /* + * Soft reset the controller. + */ + csr32w(ctlr, Cr, Rst); + delay(1); + while(csr32r(ctlr, Cr) & Rst) + delay(1); + return 0; +} + +static void +dp83820shutdown(Ether* ether) +{ +print("dp83820shutdown\n"); + dp83820detach(ether->ctlr); +} + +static int +atc93c46r(Ctlr* ctlr, int address) +{ + int data, i, mear, r, size; + + /* + * Analog Technology, Inc. ATC93C46 + * or equivalent serial EEPROM. + */ + mear = csr32r(ctlr, Mear); + mear &= ~(Eesel|Eeclk|Eedo|Eedi); + r = Eesel|mear; + +reread: + csr32w(ctlr, Mear, r); + data = 0x06; + for(i = 3-1; i >= 0; i--){ + if(data & (1<<i)) + r |= Eedi; + else + r &= ~Eedi; + csr32w(ctlr, Mear, r); + csr32w(ctlr, Mear, Eeclk|r); + microdelay(1); + csr32w(ctlr, Mear, r); + microdelay(1); + } + + /* + * First time through must work out the EEPROM size. + */ + if((size = ctlr->eepromsz) == 0) + size = 8; + + for(size = size-1; size >= 0; size--){ + if(address & (1<<size)) + r |= Eedi; + else + r &= ~Eedi; + csr32w(ctlr, Mear, r); + microdelay(1); + csr32w(ctlr, Mear, Eeclk|r); + microdelay(1); + csr32w(ctlr, Mear, r); + microdelay(1); + if(!(csr32r(ctlr, Mear) & Eedo)) + break; + } + r &= ~Eedi; + + data = 0; + for(i = 16-1; i >= 0; i--){ + csr32w(ctlr, Mear, Eeclk|r); + microdelay(1); + if(csr32r(ctlr, Mear) & Eedo) + data |= (1<<i); + csr32w(ctlr, Mear, r); + microdelay(1); + } + + csr32w(ctlr, Mear, mear); + + if(ctlr->eepromsz == 0){ + ctlr->eepromsz = 8-size; + ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort)); + goto reread; + } + + return data; +} + +static int +dp83820reset(Ctlr* ctlr) +{ + int i, r; + unsigned char sum; + + /* + * Soft reset the controller; + * read the EEPROM to get the initial settings + * of the Cfg and Gpior bits which should be cleared by + * the reset. + */ + csr32w(ctlr, Cr, Rst); + delay(1); + while(csr32r(ctlr, Cr) & Rst) + delay(1); + + atc93c46r(ctlr, 0); + if(ctlr->eeprom == nil) { + print("dp83820reset: no eeprom\n"); + return -1; + } + sum = 0; + for(i = 0; i < 0x0E; i++){ + r = atc93c46r(ctlr, i); + ctlr->eeprom[i] = r; + sum += r; + sum += r>>8; + } + + if(sum != 0){ + print("dp83820reset: bad EEPROM checksum\n"); + return -1; + } + +#ifdef notdef + csr32w(ctlr, Gpior, ctlr->eeprom[4]); + + cfg = Extstsen|Exd; + r = csr32r(ctlr, Cfg); + if(ctlr->eeprom[5] & 0x0001) + cfg |= Ext125; + if(ctlr->eeprom[5] & 0x0002) + cfg |= M64addren; + if((ctlr->eeprom[5] & 0x0004) && (r & Pci64det)) + cfg |= Data64en; + if(ctlr->eeprom[5] & 0x0008) + cfg |= T64addren; + if(!(pcicfgr16(ctlr->pcidev, PciPCR) & 0x10)) + cfg |= Mwidis; + if(ctlr->eeprom[5] & 0x0020) + cfg |= Mrmdis; + if(ctlr->eeprom[5] & 0x0080) + cfg |= Mode1000; + if(ctlr->eeprom[5] & 0x0200) + cfg |= Tbien|Mode1000; + /* + * What about RO bits we might have destroyed with Rst? + * What about Exd, Tmrtest, Extstsen, Pintctl? + * Why does it think it has detected a 64-bit bus when + * it hasn't? + */ +#else + //r = csr32r(ctlr, Cfg); + //r &= ~(Mode1000|T64addren|Data64en|M64addren); + //csr32w(ctlr, Cfg, r); + //csr32w(ctlr, Cfg, 0x2000); +#endif /* notdef */ + ctlr->cfg = csr32r(ctlr, Cfg); +print("cfg %8.8uX pcicfg %8.8uX\n", ctlr->cfg, pcicfgr32(ctlr->pcidev, PciPCR)); + ctlr->cfg &= ~(T64addren|Data64en|M64addren); + csr32w(ctlr, Cfg, ctlr->cfg); + csr32w(ctlr, Mibc, Aclr|Frz); + + return 0; +} + +static void +dp83820pci(void) +{ + int port; + Pcidev *p; + Ctlr *ctlr; + + p = nil; + while(p = pcimatch(p, 0, 0)){ + if(p->ccrb != 0x02 || p->ccru != 0) + continue; + + switch((p->did<<16)|p->vid){ + default: + continue; + case (0x0022<<16)|0x100B: /* DP83820 (Gig-NIC) */ + break; + } + + port = upamalloc(p->mem[1].bar & ~0x0F, p->mem[1].size, 0); + if(port == 0){ + print("dp83820: can't map %d @ 0x%8.8luX\n", + p->mem[1].size, p->mem[1].bar); + continue; + } + + ctlr = malloc(sizeof(Ctlr)); + ctlr->port = port; + ctlr->pcidev = p; + ctlr->id = p->did<<16 | p->vid; + + ctlr->nic = KADDR(ctlr->port); + if(dp83820reset(ctlr)){ + free(ctlr); + continue; + } + pcisetbme(p); + + if(dp83820ctlrhead != nil) + dp83820ctlrtail->next = ctlr; + else + dp83820ctlrhead = ctlr; + dp83820ctlrtail = ctlr; + } +} + +int +dp83820pnp(Ether* edev) +{ + int i; + Ctlr *ctlr; + uchar ea[Eaddrlen]; + + if(dp83820ctlrhead == nil) + dp83820pci(); + + /* + * Any adapter matches if no edev->port is supplied, + * otherwise the ports must match. + */ + for(ctlr = dp83820ctlrhead; ctlr != nil; ctlr = ctlr->next){ + if(ctlr->active) + continue; + if(edev->port == 0 || edev->port == ctlr->port){ + ctlr->active = 1; + break; + } + } + if(ctlr == nil) + return -1; + + edev->ctlr = ctlr; + edev->port = ctlr->port; + edev->irq = ctlr->pcidev->intl; + edev->tbdf = ctlr->pcidev->tbdf; + + /* + * Check if the adapter's station address is to be overridden. + * If not, read it from the EEPROM and set in ether->ea prior to + * loading the station address in the hardware. + */ + memset(ea, 0, Eaddrlen); + if(memcmp(ea, edev->ea, Eaddrlen) == 0) + for(i = 0; i < Eaddrlen/2; i++){ + edev->ea[2*i] = ctlr->eeprom[0x0C-i]; + edev->ea[2*i+1] = ctlr->eeprom[0x0C-i]>>8; + } + + edev->attach = dp83820attach; + edev->transmit = dp83820transmit; + edev->interrupt = dp83820interrupt; + edev->detach = dp83820shutdown; + return 0; +} diff --git a/os/boot/pc/etherelnk3.c b/os/boot/pc/etherelnk3.c index 618f7a1b..fe27dd92 100644 --- a/os/boot/pc/etherelnk3.c +++ b/os/boot/pc/etherelnk3.c @@ -49,7 +49,6 @@ #include "etherif.h" -#define coherence() #define XCVRDEBUG if(0)print enum { diff --git a/os/boot/pc/etherelnk3x.c b/os/boot/pc/etherelnk3x.c new file mode 100644 index 00000000..2eafdf01 --- /dev/null +++ b/os/boot/pc/etherelnk3x.c @@ -0,0 +1,1074 @@ +/* + * Etherlink III and Fast EtherLink adapters. + * To do: + * autoSelect; + * busmaster channel; + * PCMCIA; + * PCI latency timer and master enable; + * errata list. + * + * Product ID: + * 9150 ISA 3C509[B] + * 9050 ISA 3C509[B]-TP + * 9450 ISA 3C509[B]-COMBO + * 9550 ISA 3C509[B]-TPO + * + * 9350 EISA 3C579 + * 9250 EISA 3C579-TP + * + * 5920 EISA 3C592-[TP|COMBO|TPO] + * 5970 EISA 3C597-TX Fast Etherlink 10BASE-T/100BASE-TX + * 5971 EISA 3C597-T4 Fast Etherlink 10BASE-T/100BASE-T4 + * 5972 EISA 3C597-MII Fast Etherlink 10BASE-T/MII + * + * 5900 PCI 3C590-[TP|COMBO|TPO] + * 5950 PCI 3C595-TX Fast Etherlink Shared 10BASE-T/100BASE-TX + * 5951 PCI 3C595-T4 Fast Etherlink Shared 10BASE-T/100BASE-T4 + * 5952 PCI 3C595-MII Fast Etherlink 10BASE-T/MII + * + * 9058 PCMCIA 3C589[B]-[TP|COMBO] + * + * 627C MCA 3C529 + * 627D MCA 3C529-TP + */ +#include "u.h" +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" + +#include "etherif.h" + +enum { + IDport = 0x0110, /* anywhere between 0x0100 and 0x01F0 */ +}; + +enum { /* all windows */ + Command = 0x000E, + IntStatus = 0x000E, +}; + +enum { /* Commands */ + GlobalReset = 0x0000, + SelectRegisterWindow = 0x0001, + EnableDcConverter = 0x0002, + RxDisable = 0x0003, + RxEnable = 0x0004, + RxReset = 0x0005, + TxDone = 0x0007, + RxDiscard = 0x0008, + TxEnable = 0x0009, + TxDisable = 0x000A, + TxReset = 0x000B, + RequestInterrupt = 0x000C, + AcknowledgeInterrupt = 0x000D, + SetInterruptEnable = 0x000E, + SetIndicationEnable = 0x000F, /* SetReadZeroMask */ + SetRxFilter = 0x0010, + SetRxEarlyThresh = 0x0011, + SetTxAvailableThresh = 0x0012, + SetTxStartThresh = 0x0013, + StartDma = 0x0014, /* initiate busmaster operation */ + StatisticsEnable = 0x0015, + StatisticsDisable = 0x0016, + DisableDcConverter = 0x0017, + SetTxReclaimThresh = 0x0018, /* PIO-only adapters */ + PowerUp = 0x001B, /* not all adapters */ + PowerDownFull = 0x001C, /* not all adapters */ + PowerAuto = 0x001D, /* not all adapters */ +}; + +enum { /* (Global|Rx|Tx)Reset command bits */ + tpAuiReset = 0x0001, /* 10BaseT and AUI transceivers */ + endecReset = 0x0002, /* internal Ethernet encoder/decoder */ + networkReset = 0x0004, /* network interface logic */ + fifoReset = 0x0008, /* FIFO control logic */ + aismReset = 0x0010, /* autoinitialise state-machine logic */ + hostReset = 0x0020, /* bus interface logic */ + dmaReset = 0x0040, /* bus master logic */ + vcoReset = 0x0080, /* on-board 10Mbps VCO */ + + resetMask = 0x00FF, +}; + +enum { /* SetRxFilter command bits */ + receiveIndividual = 0x0001, /* match station address */ + receiveMulticast = 0x0002, + receiveBroadcast = 0x0004, + receiveAllFrames = 0x0008, /* promiscuous */ +}; + +enum { /* StartDma command bits */ + Upload = 0x0000, /* transfer data from adapter to memory */ + Download = 0x0001, /* transfer data from memory to adapter */ +}; + +enum { /* IntStatus bits */ + interruptLatch = 0x0001, + hostError = 0x0002, /* Adapter Failure */ + txComplete = 0x0004, + txAvailable = 0x0008, + rxComplete = 0x0010, + rxEarly = 0x0020, + intRequested = 0x0040, + updateStats = 0x0080, + transferInt = 0x0100, /* Bus Master Transfer Complete */ + busMasterInProgress = 0x0800, + commandInProgress = 0x1000, + + interruptMask = 0x01FE, +}; + +#define COMMAND(port, cmd, a) outs((port)+Command, ((cmd)<<11)|(a)) +#define STATUS(port) ins((port)+IntStatus) + +enum { /* Window 0 - setup */ + Wsetup = 0x0000, + /* registers */ + ManufacturerID = 0x0000, /* 3C5[08]*, 3C59[27] */ + ProductID = 0x0002, /* 3C5[08]*, 3C59[27] */ + ConfigControl = 0x0004, /* 3C5[08]*, 3C59[27] */ + AddressConfig = 0x0006, /* 3C5[08]*, 3C59[27] */ + ResourceConfig = 0x0008, /* 3C5[08]*, 3C59[27] */ + EepromCommand = 0x000A, + EepromData = 0x000C, + /* AddressConfig Bits */ + autoSelect9 = 0x0080, + xcvrMask9 = 0xC000, + /* ConfigControl bits */ + Ena = 0x0001, + /* EepromCommand bits */ + EepromReadRegister = 0x0080, + EepromBusy = 0x8000, +}; + +#define EEPROMCMD(port, cmd, a) outs((port)+EepromCommand, (cmd)|(a)) +#define EEPROMBUSY(port) (ins((port)+EepromCommand) & EepromBusy) +#define EEPROMDATA(port) ins((port)+EepromData) + +enum { /* Window 1 - operating set */ + Wop = 0x0001, + /* registers */ + Fifo = 0x0000, + RxError = 0x0004, /* 3C59[0257] only */ + RxStatus = 0x0008, + Timer = 0x000A, + TxStatus = 0x000B, + TxFree = 0x000C, + /* RxError bits */ + rxOverrun = 0x0001, + runtFrame = 0x0002, + alignmentError = 0x0004, /* Framing */ + crcError = 0x0008, + oversizedFrame = 0x0010, + dribbleBits = 0x0080, + /* RxStatus bits */ + rxBytes = 0x1FFF, /* 3C59[0257] mask */ + rxBytes9 = 0x07FF, /* 3C5[078]9 mask */ + rxError9 = 0x3800, /* 3C5[078]9 error mask */ + rxOverrun9 = 0x0000, + oversizedFrame9 = 0x0800, + dribbleBits9 = 0x1000, + runtFrame9 = 0x1800, + alignmentError9 = 0x2000, /* Framing */ + crcError9 = 0x2800, + rxError = 0x4000, + rxIncomplete = 0x8000, + /* TxStatus Bits */ + txStatusOverflow = 0x0004, + maxCollisions = 0x0008, + txUnderrun = 0x0010, + txJabber = 0x0020, + interruptRequested = 0x0040, + txStatusComplete = 0x0080, +}; + +enum { /* Window 2 - station address */ + Wstation = 0x0002, +}; + +enum { /* Window 3 - FIFO management */ + Wfifo = 0x0003, + /* registers */ + InternalConfig = 0x0000, /* 3C509B, 3C589, 3C59[0257] */ + OtherInt = 0x0004, /* 3C59[0257] */ + RomControl = 0x0006, /* 3C509B, 3C59[27] */ + MacControl = 0x0006, /* 3C59[0257] */ + ResetOptions = 0x0008, /* 3C59[0257] */ + RxFree = 0x000A, + /* InternalConfig bits */ + disableBadSsdDetect = 0x00000100, + ramLocation = 0x00000200, /* 0 external, 1 internal */ + ramPartition5to3 = 0x00000000, + ramPartition3to1 = 0x00010000, + ramPartition1to1 = 0x00020000, + ramPartition3to5 = 0x00030000, + ramPartitionMask = 0x00030000, + xcvr10BaseT = 0x00000000, + xcvrAui = 0x00100000, /* 10BASE5 */ + xcvr10Base2 = 0x00300000, + xcvr100BaseTX = 0x00400000, + xcvr100BaseFX = 0x00500000, + xcvrMii = 0x00600000, + xcvrMask = 0x00700000, + autoSelect = 0x01000000, + /* MacControl bits */ + deferExtendEnable = 0x0001, + deferTimerSelect = 0x001E, /* mask */ + fullDuplexEnable = 0x0020, + allowLargePackets = 0x0040, + /* ResetOptions bits */ + baseT4Available = 0x0001, + baseTXAvailable = 0x0002, + baseFXAvailable = 0x0004, + base10TAvailable = 0x0008, + coaxAvailable = 0x0010, + auiAvailable = 0x0020, + miiConnector = 0x0040, +}; + +enum { /* Window 4 - diagnostic */ + Wdiagnostic = 0x0004, + /* registers */ + VcoDiagnostic = 0x0002, + FifoDiagnostic = 0x0004, + NetworkDiagnostic = 0x0006, + PhysicalMgmt = 0x0008, + MediaStatus = 0x000A, + BadSSD = 0x000C, + /* FifoDiagnostic bits */ + txOverrun = 0x0400, + rxUnderrun = 0x2000, + receiving = 0x8000, + /* MediaStatus bits */ + dataRate100 = 0x0002, + crcStripDisable = 0x0004, + enableSqeStats = 0x0008, + collisionDetect = 0x0010, + carrierSense = 0x0020, + jabberGuardEnable = 0x0040, + linkBeatEnable = 0x0080, + jabberDetect = 0x0200, + polarityReversed = 0x0400, + linkBeatDetect = 0x0800, + txInProg = 0x1000, + dcConverterEnabled = 0x4000, + auiDisable = 0x8000, +}; + +enum { /* Window 5 - internal state */ + Wstate = 0x0005, + /* registers */ + TxStartThresh = 0x0000, + TxAvalableThresh = 0x0002, + RxEarlyThresh = 0x0006, + RxFilter = 0x0008, + InterruptEnable = 0x000A, + IndicationEnable = 0x000C, +}; + +enum { /* Window 6 - statistics */ + Wstatistics = 0x0006, + /* registers */ + CarrierLost = 0x0000, + SqeErrors = 0x0001, + MultipleColls = 0x0002, + SingleCollFrames = 0x0003, + LateCollisions = 0x0004, + RxOverruns = 0x0005, + FramesXmittedOk = 0x0006, + FramesRcvdOk = 0x0007, + FramesDeferred = 0x0008, + UpperFramesOk = 0x0009, + BytesRcvdOk = 0x000A, + BytesXmittedOk = 0x000C, +}; + +enum { /* Window 7 - bus master operations */ + Wmaster = 0x0007, + /* registers */ + MasterAddress = 0x0000, + MasterLen = 0x0006, + MasterStatus = 0x000C, + /* MasterStatus bits */ + masterAbort = 0x0001, + targetAbort = 0x0002, + targetRetry = 0x0004, + targetDisc = 0x0008, + masterDownload = 0x1000, + masterUpload = 0x4000, + masterInProgress = 0x8000, + + masterMask = 0xD00F, +}; + +typedef struct { + int txthreshold; +} Ctlr; + +static void +attach(Ether* ether) +{ + int port, x; + + port = ether->port; + + /* + * Set the receiver packet filter for this and broadcast addresses, + * set the interrupt masks for all interrupts, enable the receiver + * and transmitter. + */ + x = receiveBroadcast|receiveIndividual; + COMMAND(port, SetRxFilter, x); + + x = interruptMask|interruptLatch; + COMMAND(port, SetIndicationEnable, x); + COMMAND(port, SetInterruptEnable, x); + + COMMAND(port, RxEnable, 0); + COMMAND(port, TxEnable, 0); +} + +static void +transmit(Ether* ether) +{ + int port, len; + RingBuf *tb; + + /* + * Attempt to top-up the transmit FIFO. If there's room simply + * stuff in the packet length (unpadded to a dword boundary), the + * packet data (padded) and remove the packet from the queue. + * If there's no room post an interrupt for when there is. + * This routine is called both from the top level and from interrupt + * level. + */ + port = ether->port; + for(tb = ðer->tb[ether->ti]; tb->owner == Interface; tb = ðer->tb[ether->ti]){ + len = ROUNDUP(tb->len, 4); + if(len+4 <= ins(port+TxFree)){ + outl(port+Fifo, tb->len); + outsl(port+Fifo, tb->pkt, len/4); + tb->owner = Host; + ether->ti = NEXT(ether->ti, ether->ntb); + } + else{ + COMMAND(port, SetTxAvailableThresh, len); + break; + } + } +} + +static void +receive(Ether* ether) +{ + int len, port, rxstatus; + RingBuf *rb; + + port = ether->port; + + while(((rxstatus = ins(port+RxStatus)) & rxIncomplete) == 0){ + /* + * If there was an error, throw it away and continue. + * The 3C5[078]9 has the error info in the status register + * and the 3C59[0257] implement a separate RxError register. + */ + if((rxstatus & rxError) == 0){ + /* + * Packet received. Read it into the next free + * ring buffer, if any. Must read len bytes padded + * to a doubleword, can be picked out 32-bits at + * a time. The CRC is already stripped off. + */ + rb = ðer->rb[ether->ri]; + if(rb->owner == Interface){ + len = (rxstatus & rxBytes9); + rb->len = len; + insl(port+Fifo, rb->pkt, HOWMANY(len, 4)); + + rb->owner = Host; + ether->ri = NEXT(ether->ri, ether->nrb); + } + } + + /* + * All done, discard the packet. + */ + COMMAND(port, RxDiscard, 0); + while(STATUS(port) & commandInProgress) + ; + } +} + +static void +statistics(Ether* ether) +{ + int i, port, w; + + port = ether->port; + w = (STATUS(port)>>13) & 0x07; + COMMAND(port, SelectRegisterWindow, Wop); + COMMAND(port, SelectRegisterWindow, Wstatistics); + + for(i = 0; i < 0x0A; i++) + inb(port+i); + ins(port+BytesRcvdOk); + ins(port+BytesXmittedOk); + + COMMAND(port, SelectRegisterWindow, w); +} + +static void +interrupt(Ureg*, void* arg) +{ + Ether *ether; + int port, status, txstatus, w, x; + Ctlr *ctlr; + + ether = arg; + port = ether->port; + ctlr = ether->ctlr; + + w = (STATUS(port)>>13) & 0x07; + COMMAND(port, SelectRegisterWindow, Wop); + + for(;;){ + /* + * Clear the interrupt latch. + * It's possible to receive a packet and for another + * to become complete before exiting the interrupt + * handler so this must be done first to ensure another + * interrupt will occur. + */ + COMMAND(port, AcknowledgeInterrupt, interruptLatch); + status = STATUS(port); + if((status & interruptMask) == 0) + break; + + if(status & hostError){ + /* + * Adapter failure, try to find out why, reset if + * necessary. What happens if Tx is active and a reset + * occurs, need to retransmit? This probably isn't right. + */ + COMMAND(port, SelectRegisterWindow, Wdiagnostic); + x = ins(port+FifoDiagnostic); + COMMAND(port, SelectRegisterWindow, Wop); + print("elnk3#%d: status 0x%uX, diag 0x%uX\n", + ether->ctlrno, status, x); + + if(x & txOverrun){ + COMMAND(port, TxReset, 0); + COMMAND(port, TxEnable, 0); + } + + if(x & rxUnderrun){ + /* + * This shouldn't happen... + * Need to restart any busmastering? + */ + COMMAND(port, RxReset, 0); + while(STATUS(port) & commandInProgress) + ; + COMMAND(port, RxEnable, 0); + } + + status &= ~hostError; + } + + if(status & (transferInt|rxComplete)){ + receive(ether); + status &= ~(transferInt|rxComplete); + } + + if(status & txComplete){ + /* + * Pop the TxStatus stack, accumulating errors. + * Adjust the TX start threshold if there was an underrun. + * If there was a Jabber or Underrun error, reset + * the transmitter. + * For all conditions enable the transmitter. + */ + txstatus = 0; + do{ + if(x = inb(port+TxStatus)) + outb(port+TxStatus, 0); + txstatus |= x; + }while(STATUS(port) & txComplete); + + if(txstatus & txUnderrun){ + COMMAND(port, SelectRegisterWindow, Wdiagnostic); + while(ins(port+MediaStatus) & txInProg) + ; + COMMAND(port, SelectRegisterWindow, Wop); + if(ctlr->txthreshold < ETHERMAXTU) + ctlr->txthreshold += ETHERMINTU; + } + + if(txstatus & (txJabber|txUnderrun)){ + COMMAND(port, TxReset, 0); + while(STATUS(port) & commandInProgress) + ; + COMMAND(port, SetTxStartThresh, ctlr->txthreshold); + } + COMMAND(port, TxEnable, 0); + status &= ~txComplete; + status |= txAvailable; + } + + if(status & txAvailable){ + COMMAND(port, AcknowledgeInterrupt, txAvailable); + transmit(ether); + status &= ~txAvailable; + } + + if(status & updateStats){ + statistics(ether); + status &= ~updateStats; + } + + /* + * Panic if there are any interrupts not dealt with. + */ + if(status & interruptMask) + panic("elnk3#%d: interrupt mask 0x%uX\n", ether->ctlrno, status); + } + + COMMAND(port, SelectRegisterWindow, w); +} + +typedef struct Adapter { + int port; + int irq; + int tbdf; +} Adapter; +static Block* adapter; + +static void +tcmadapter(int port, int irq, int tbdf) +{ + Block *bp; + Adapter *ap; + + bp = allocb(sizeof(Adapter)); + ap = (Adapter*)bp->rp; + ap->port = port; + ap->irq = irq; + ap->tbdf = tbdf; + + bp->next = adapter; + adapter = bp; +} + +/* + * Write two 0 bytes to identify the IDport and then reset the + * ID sequence. Then send the ID sequence to the card to get + * the card into command state. + */ +static void +idseq(void) +{ + int i; + uchar al; + static int reset, untag; + + /* + * One time only: + * reset any adapters listening + */ + if(reset == 0){ + outb(IDport, 0); + outb(IDport, 0); + outb(IDport, 0xC0); + delay(20); + reset = 1; + } + + outb(IDport, 0); + outb(IDport, 0); + for(al = 0xFF, i = 0; i < 255; i++){ + outb(IDport, al); + if(al & 0x80){ + al <<= 1; + al ^= 0xCF; + } + else + al <<= 1; + } + + /* + * One time only: + * write ID sequence to get the attention of all adapters; + * untag all adapters. + * If we do a global reset here on all adapters we'll confuse any + * ISA cards configured for EISA mode. + */ + if(untag == 0){ + outb(IDport, 0xD0); + untag = 1; + } +} + +static ulong +activate(void) +{ + int i; + ushort x, acr; + + /* + * Do the little configuration dance: + * + * 2. write the ID sequence to get to command state. + */ + idseq(); + + /* + * 3. Read the Manufacturer ID from the EEPROM. + * This is done by writing the IDPort with 0x87 (0x80 + * is the 'read EEPROM' command, 0x07 is the offset of + * the Manufacturer ID field in the EEPROM). + * The data comes back 1 bit at a time. + * We seem to need a delay here between reading the bits. + * + * If the ID doesn't match, there are no more adapters. + */ + outb(IDport, 0x87); + delay(20); + for(x = 0, i = 0; i < 16; i++){ + delay(20); + x <<= 1; + x |= inb(IDport) & 0x01; + } + if(x != 0x6D50) + return 0; + + /* + * 3. Read the Address Configuration from the EEPROM. + * The Address Configuration field is at offset 0x08 in the EEPROM). + */ + outb(IDport, 0x88); + for(acr = 0, i = 0; i < 16; i++){ + delay(20); + acr <<= 1; + acr |= inb(IDport) & 0x01; + } + + return (acr & 0x1F)*0x10 + 0x200; +} + +#ifdef notjustpcmcia +static void +tcm509isa(void) +{ + int irq, port; + + /* + * Attempt to activate all adapters. If adapter is set for + * EISA mode (0x3F0), tag it and ignore. Otherwise, activate + * it fully. + */ + while(port = activate()){ + /* + * 6. Tag the adapter so it won't respond in future. + */ + outb(IDport, 0xD1); + if(port == 0x3F0) + continue; + + /* + * 6. Activate the adapter by writing the Activate command + * (0xFF). + */ + outb(IDport, 0xFF); + delay(20); + + /* + * 8. Can now talk to the adapter's I/O base addresses. + * Use the I/O base address from the acr just read. + * + * Enable the adapter and clear out any lingering status + * and interrupts. + */ + while(STATUS(port) & commandInProgress) + ; + COMMAND(port, SelectRegisterWindow, Wsetup); + outs(port+ConfigControl, Ena); + + COMMAND(port, TxReset, 0); + COMMAND(port, RxReset, 0); + COMMAND(port, AcknowledgeInterrupt, 0xFF); + + irq = (ins(port+ResourceConfig)>>12) & 0x0F; + tcmadapter(port, irq, BUSUNKNOWN); + } +} + +static void +tcm5XXeisa(void) +{ + ushort x; + int irq, port, slot; + + /* + * Check if this is an EISA machine. + * If not, nothing to do. + */ + if(strncmp((char*)(KZERO|0xFFFD9), "EISA", 4)) + return; + + /* + * Continue through the EISA slots looking for a match on both + * 3COM as the manufacturer and 3C579-* or 3C59[27]-* as the product. + * If an adapter is found, select window 0, enable it and clear + * out any lingering status and interrupts. + */ + for(slot = 1; slot < MaxEISA; slot++){ + port = slot*0x1000; + if(ins(port+0xC80+ManufacturerID) != 0x6D50) + continue; + x = ins(port+0xC80+ProductID); + if((x & 0xF0FF) != 0x9050 && (x & 0xFF00) != 0x5900) + continue; + + COMMAND(port, SelectRegisterWindow, Wsetup); + outs(port+ConfigControl, Ena); + + COMMAND(port, TxReset, 0); + COMMAND(port, RxReset, 0); + COMMAND(port, AcknowledgeInterrupt, 0xFF); + + irq = (ins(port+ResourceConfig)>>12) & 0x0F; + tcmadapter(port, irq, BUSUNKNOWN); + } +} + +static void +tcm59Xpci(void) +{ + Pcidev *p; + int irq, port; + + p = nil; + while(p = pcimatch(p, 0x10B7, 0)){ + port = p->mem[0].bar & ~0x01; + irq = p->intl; + COMMAND(port, GlobalReset, 0); + while(STATUS(port) & commandInProgress) + ; + + tcmadapter(port, irq, p->tbdf); + } +} +#endif /* notjustpcmcia */ + +static char* tcmpcmcia[] = { + "3C589", /* 3COM 589[ABCD] */ + "3C562", /* 3COM 562 */ + "589E", /* 3COM Megahertz 589E */ + nil, +}; + +static int +tcm5XXpcmcia(Ether* ether) +{ + int i; + + for(i = 0; tcmpcmcia[i] != nil; i++){ + if(!cistrcmp(ether->type, tcmpcmcia[i])) + return ether->port; + } + + return 0; +} + +static int +autoselect(int port, int rxstatus9) +{ + int media, x; + + /* + * Pathetic attempt at automatic media selection. + * Really just to get the Fast Etherlink 10BASE-T/100BASE-TX + * cards operational. + */ + media = auiAvailable|coaxAvailable|base10TAvailable; + if(rxstatus9 == 0){ + COMMAND(port, SelectRegisterWindow, Wfifo); + media = ins(port+ResetOptions); + } + + if(media & miiConnector) + return xcvrMii; + + if(media & baseTXAvailable){ + /* + * Must have InternalConfig register. + */ + COMMAND(port, SelectRegisterWindow, Wfifo); + x = inl(port+InternalConfig) & ~xcvrMask; + x |= xcvr100BaseTX; + outl(port+InternalConfig, x); + COMMAND(port, TxReset, 0); + while(STATUS(port) & commandInProgress) + ; + COMMAND(port, RxReset, 0); + while(STATUS(port) & commandInProgress) + ; + + COMMAND(port, SelectRegisterWindow, Wdiagnostic); + x = ins(port+MediaStatus) & ~(dcConverterEnabled|jabberGuardEnable); + outs(port+MediaStatus, linkBeatEnable|x); + delay(10); + +{ int i, v; + for(i = 0; i < 10000; i++){ + v = ins(port+MediaStatus); + if(v & linkBeatDetect){ + print("count %d v %uX\n", i, v); + return xcvr100BaseTX; + } + delay(1); + } +print("count %d v %uX\n", i, ins(port+MediaStatus)); +} + if(ins(port+MediaStatus) & linkBeatDetect) + return xcvr100BaseTX; + outs(port+MediaStatus, x); + } + + if(media & base10TAvailable){ + if(rxstatus9 == 0){ + COMMAND(port, SelectRegisterWindow, Wfifo); + x = inl(port+InternalConfig) & ~xcvrMask; + x |= xcvr10BaseT; + outl(port+InternalConfig, x); + } + else{ + COMMAND(port, SelectRegisterWindow, Wsetup); + x = ins(port+AddressConfig) & ~xcvrMask9; + x |= (xcvr10BaseT>>20)<<14; + outs(port+AddressConfig, x); + } + COMMAND(port, TxReset, 0); + while(STATUS(port) & commandInProgress) + ; + COMMAND(port, RxReset, 0); + while(STATUS(port) & commandInProgress) + ; + + COMMAND(port, SelectRegisterWindow, Wdiagnostic); + x = ins(port+MediaStatus) & ~dcConverterEnabled; + outs(port+MediaStatus, linkBeatEnable|jabberGuardEnable|x); + delay(10); + + if(ins(port+MediaStatus) & linkBeatDetect) + return xcvr10BaseT; + outs(port+MediaStatus, x); + } + + /* + * Botch. + */ + return autoSelect; +} + +static int +eepromdata(int port, int offset) +{ + COMMAND(port, SelectRegisterWindow, Wsetup); + while(EEPROMBUSY(port)) + ; + EEPROMCMD(port, EepromReadRegister, offset); + while(EEPROMBUSY(port)) + ; + return EEPROMDATA(port); +} + +int +elnk3reset(Ether* ether) +{ + int did, i, port, rxstatus9, x, xcvr; + Block *bp, **bpp; + Adapter *ap; + uchar ea[Eaddrlen]; + Ctlr *ctlr; +#ifdef notjustpcmcia + static int scandone; + + /* + * Scan for adapter on PCI, EISA and finally + * using the little ISA configuration dance. + */ + if(scandone == 0){ + tcm59Xpci(); + tcm5XXeisa(); + tcm509isa(); + scandone = 1; + } +#endif /* notjustpcmcia */ + + /* + * Any adapter matches if no ether->port is supplied, + * otherwise the ports must match. + */ + port = 0; + bpp = &adapter; + for(bp = *bpp; bp; bp = bp->next){ + ap = (Adapter*)bp->rp; + if(ether->port == 0 || ether->port == ap->port){ + port = ap->port; + ether->irq = ap->irq; + ether->tbdf = ap->tbdf; + *bpp = bp->next; + freeb(bp); + break; + } + bpp = &bp->next; + } + if(port == 0 && (port = tcm5XXpcmcia(ether)) == 0) + return -1; + + /* + * Read the DeviceID from the EEPROM, it's at offset 0x03, + * and do something depending on capabilities. + */ + switch(did = eepromdata(port, 0x03)){ + + case 0x9000: + case 0x9001: + case 0x9050: + case 0x9051: + if(BUSTYPE(ether->tbdf) != BusPCI) + goto buggery; + goto vortex; + + case 0x5900: + case 0x5920: + case 0x5950: + case 0x5951: + case 0x5952: + case 0x5970: + case 0x5971: + case 0x5972: + vortex: + COMMAND(port, SelectRegisterWindow, Wfifo); + xcvr = inl(port+InternalConfig) & (autoSelect|xcvrMask); + rxstatus9 = 0; + break; + + buggery: + default: + COMMAND(port, SelectRegisterWindow, Wsetup); + x = ins(port+AddressConfig); + xcvr = ((x & xcvrMask9)>>14)<<20; + if(x & autoSelect9) + xcvr |= autoSelect; + rxstatus9 = 1; + break; + } + USED(did); + + /* + * Check if the adapter's station address is to be overridden. + * If not, read it from the EEPROM and set in ether->ea prior to loading the + * station address in Wstation. The EEPROM returns 16-bits at a time. + */ + memset(ea, 0, Eaddrlen); + if(memcmp(ea, ether->ea, Eaddrlen) == 0){ + for(i = 0; i < Eaddrlen/2; i++){ + x = eepromdata(port, i); + ether->ea[2*i] = x>>8; + ether->ea[2*i+1] = x; + } + } + + COMMAND(port, SelectRegisterWindow, Wstation); + for(i = 0; i < Eaddrlen; i++) + outb(port+i, ether->ea[i]); + + /* + * Enable the transceiver if necessary. + */ + if(xcvr & autoSelect) + xcvr = autoselect(port, rxstatus9); + switch(xcvr){ + + case xcvrMii: + break; + + case xcvr100BaseTX: + case xcvr100BaseFX: + COMMAND(port, SelectRegisterWindow, Wfifo); + x = inl(port+InternalConfig) & ~ramPartitionMask; + outl(port+InternalConfig, x|ramPartition1to1); + + COMMAND(port, SelectRegisterWindow, Wdiagnostic); + x = ins(port+MediaStatus) & ~(dcConverterEnabled|jabberGuardEnable); + x |= linkBeatEnable; + outs(port+MediaStatus, x); + break; + + case xcvr10BaseT: + /* + * Enable Link Beat and Jabber to start the + * transceiver. + */ + COMMAND(port, SelectRegisterWindow, Wdiagnostic); + x = ins(port+MediaStatus) & ~dcConverterEnabled; + x |= linkBeatEnable|jabberGuardEnable; + outs(port+MediaStatus, x); + break; + + case xcvr10Base2: + COMMAND(port, SelectRegisterWindow, Wdiagnostic); + x = ins(port+MediaStatus) & ~(linkBeatEnable|jabberGuardEnable); + outs(port+MediaStatus, x); + + /* + * Start the DC-DC converter. + * Wait > 800 microseconds. + */ + COMMAND(port, EnableDcConverter, 0); + delay(1); + break; + } + + /* + * Wop is the normal operating register set. + * The 3C59[0257] adapters allow access to more than one register window + * at a time, but there are situations where switching still needs to be + * done, so just do it. + * Clear out any lingering Tx status. + */ + COMMAND(port, SelectRegisterWindow, Wop); + while(inb(port+TxStatus)) + outb(port+TxStatus, 0); + + /* + * Allocate a controller structure and start + * to initialise it. + */ + ether->ctlr = malloc(sizeof(Ctlr)); + ctlr = ether->ctlr; + memset(ctlr, 0, sizeof(Ctlr)); + + /* + * Set a base TxStartThresh which will be incremented + * if any txUnderrun errors occur and ensure no RxEarly + * interrupts happen. + */ + ctlr->txthreshold = ETHERMINTU; + COMMAND(port, SetTxStartThresh, ETHERMINTU); + COMMAND(port, SetRxEarlyThresh, ETHERMAXTU); + + /* + * Set up the software configuration. + */ + ether->port = port; + ether->attach = attach; + ether->transmit = transmit; + ether->interrupt = interrupt; + + return 0; +} diff --git a/os/boot/pc/etherga620.c b/os/boot/pc/etherga620.c new file mode 100644 index 00000000..013602bc --- /dev/null +++ b/os/boot/pc/etherga620.c @@ -0,0 +1,1147 @@ +/* + * bootstrap driver for + * Netgear GA620 Gigabit Ethernet Card. + * Specific for the Alteon Tigon 2 and Intel Pentium or later. + * To Do: + * cache alignment for PCI Write-and-Invalidate + * mini ring (what size)? + * tune coalescing values + * statistics formatting + * don't update Spi if nothing to send + * receive ring alignment + * watchdog for link management? + */ +#include "u.h" +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" + +#define malign(n) xspanalloc((n), 32, 0) + +#include "etherif.h" +#include "etherga620fw.h" + +enum { + Mhc = 0x0040, /* Miscellaneous Host Control */ + Mlc = 0x0044, /* Miscellaneous Local Control */ + Mc = 0x0050, /* Miscellaneous Configuration */ + Ps = 0x005C, /* PCI State */ + Wba = 0x0068, /* Window Base Address */ + Wd = 0x006C, /* Window Data */ + + DMAas = 0x011C, /* DMA Assist State */ + + CPUAstate = 0x0140, /* CPU A State */ + CPUApc = 0x0144, /* CPU A Programme Counter */ + + CPUBstate = 0x0240, /* CPU B State */ + + Hi = 0x0504, /* Host In Interrupt Handler */ + Cpi = 0x050C, /* Command Producer Index */ + Spi = 0x0514, /* Send Producer Index */ + Rspi = 0x051C, /* Receive Standard Producer Index */ + Rjpi = 0x0524, /* Receive Jumbo Producer Index */ + Rmpi = 0x052C, /* Receive Mini Producer Index */ + + Mac = 0x0600, /* MAC Address */ + Gip = 0x0608, /* General Information Pointer */ + Om = 0x0618, /* Operating Mode */ + DMArc = 0x061C, /* DMA Read Configuration */ + DMAwc = 0x0620, /* DMA Write Configuration */ + Tbr = 0x0624, /* Transmit Buffer Ratio */ + Eci = 0x0628, /* Event Consumer Index */ + Cci = 0x062C, /* Command Consumer Index */ + + Rct = 0x0630, /* Receive Coalesced Ticks */ + Sct = 0x0634, /* Send Coalesced Ticks */ + St = 0x0638, /* Stat Ticks */ + SmcBD = 0x063C, /* Send Max. Coalesced BDs */ + RmcBD = 0x0640, /* Receive Max. Coalesced BDs */ + Nt = 0x0644, /* NIC Tracing */ + Gln = 0x0648, /* Gigabit Link Negotiation */ + Fln = 0x064C, /* 10/100 Link Negotiation */ + Ifx = 0x065C, /* Interface Index */ + IfMTU = 0x0660, /* Interface MTU */ + Mi = 0x0664, /* Mask Interrupts */ + Gls = 0x0668, /* Gigabit Link State */ + Fls = 0x066C, /* 10/100 Link State */ + + Cr = 0x0700, /* Command Ring */ + + Lmw = 0x0800, /* Local Memory Window */ +}; + +enum { /* Mhc */ + Is = 0x00000001, /* Interrupt State */ + Ci = 0x00000002, /* Clear Interrupt */ + Hr = 0x00000008, /* Hard Reset */ + Eebs = 0x00000010, /* Enable Endian Byte Swap */ + Eews = 0x00000020, /* Enable Endian Word (64-bit) swap */ + Mpio = 0x00000040, /* Mask PCI Interrupt Output */ +}; + +enum { /* Mlc */ + SRAM512 = 0x00000200, /* SRAM Bank Size of 512KB */ + SRAMmask = 0x00000300, + EEclk = 0x00100000, /* Serial EEPROM Clock Output */ + EEdoe = 0x00200000, /* Serial EEPROM Data Out Enable */ + EEdo = 0x00400000, /* Serial EEPROM Data Out Value */ + EEdi = 0x00800000, /* Serial EEPROM Data Input */ +}; + +enum { /* Mc */ + SyncSRAM = 0x00100000, /* Set Synchronous SRAM Timing */ +}; + +enum { /* Ps */ + PCIwm32 = 0x000000C0, /* Write Max DMA 32 */ + PCImrm = 0x00020000, /* Use Memory Read Multiple Command */ + PCI66 = 0x00080000, + PCI32 = 0x00100000, + PCIrcmd = 0x06000000, /* PCI Read Command */ + PCIwcmd = 0x70000000, /* PCI Write Command */ +}; + +enum { /* CPUAstate */ + CPUrf = 0x00000010, /* ROM Fail */ + CPUhalt = 0x00010000, /* Halt the internal CPU */ + CPUhie = 0x00040000, /* HALT instruction executed */ +}; + +enum { /* Om */ + BswapBD = 0x00000002, /* Byte Swap Buffer Descriptors */ + WswapBD = 0x00000004, /* Word Swap Buffer Descriptors */ + Warn = 0x00000008, + BswapDMA = 0x00000010, /* Byte Swap DMA Data */ + Only1DMA = 0x00000040, /* Only One DMA Active at a time */ + NoJFrag = 0x00000200, /* Don't Fragment Jumbo Frames */ + Fatal = 0x40000000, +}; + +enum { /* Lmw */ + Lmwsz = 2*1024, /* Local Memory Window Size */ + + /* + * legal values are 0x3800 iff Nsr is 128, 0x3000 iff Nsr is 256, + * or 0x2000 iff Nsr is 512. + */ + Sr = 0x3800, /* Send Ring (accessed via Lmw) */ +}; + +enum { /* Link */ + Lpref = 0x00008000, /* Preferred Link */ + L10MB = 0x00010000, + L100MB = 0x00020000, + L1000MB = 0x00040000, + Lfd = 0x00080000, /* Full Duplex */ + Lhd = 0x00100000, /* Half Duplex */ + Lefc = 0x00200000, /* Emit Flow Control Packets */ + Lofc = 0x00800000, /* Obey Flow Control Packets */ + Lean = 0x20000000, /* Enable Autonegotiation/Sensing */ + Le = 0x40000000, /* Link Enable */ +}; + +typedef struct Host64 { + uint hi; + uint lo; +} Host64; + +typedef struct Ere { /* Event Ring Element */ + int event; /* event<<24 | code<<12 | index */ + int unused; +} Ere; + +typedef int Cmd; /* cmd<<24 | flags<<12 | index */ + +typedef struct Rbd { /* Receive Buffer Descriptor */ + Host64 addr; + int indexlen; /* ring-index<<16 | buffer-length */ + int flags; /* only lower 16-bits */ + int checksum; /* ip<<16 |tcp/udp */ + int error; /* only upper 16-bits */ + int reserved; + void* opaque; /* passed to receive return ring */ +} Rbd; + +typedef struct Sbd { /* Send Buffer Descriptor */ + Host64 addr; + int lenflags; /* len<<16 |flags */ + int reserved; +} Sbd; + +enum { /* Buffer Descriptor Flags */ + Fend = 0x00000004, /* Frame Ends in this Buffer */ + Frjr = 0x00000010, /* Receive Jumbo Ring Buffer */ + Funicast = 0x00000020, /* Unicast packet (2-bit field) */ + Fmulticast = 0x00000040, /* Multicast packet */ + Fbroadcast = 0x00000060, /* Broadcast packet */ + Ferror = 0x00000400, /* Frame Has Error */ + Frmr = 0x00001000, /* Receive Mini Ring Buffer */ +}; + +enum { /* Buffer Error Flags */ + Ecrc = 0x00010000, /* bad CRC */ + Ecollision = 0x00020000, /* collision */ + Elink = 0x00040000, /* link lost */ + Ephy = 0x00080000, /* unspecified PHY frame decode error */ + Eodd = 0x00100000, /* odd number of nibbles */ + Emac = 0x00200000, /* unspecified MAC abort */ + Elen64 = 0x00400000, /* short packet */ + Eresources = 0x00800000, /* MAC out of internal resources */ + Egiant = 0x01000000, /* packet too big */ +}; + +typedef struct Rcb { /* Ring Control Block */ + Host64 addr; /* points to the Rbd ring */ + int control; /* max_len<<16 |flags */ + int unused; +} Rcb; + +enum { + TcpUdpCksum = 0x0001, /* Perform TCP or UDP checksum */ + IpCksum = 0x0002, /* Perform IP checksum */ + NoPseudoHdrCksum= 0x0008, /* Don't include the pseudo header */ + VlanAssist = 0x0010, /* Enable VLAN tagging */ + CoalUpdateOnly = 0x0020, /* Coalesce transmit interrupts */ + HostRing = 0x0040, /* Sr in host memory */ + SnapCksum = 0x0080, /* Parse + offload 802.3 SNAP frames */ + UseExtRxBd = 0x0100, /* Extended Rbd for Jumbo frames */ + RingDisabled = 0x0200, /* Jumbo or Mini RCB only */ +}; + +typedef struct Gib { /* General Information Block */ + int statistics[256]; /* Statistics */ + Rcb ercb; /* Event Ring */ + Rcb crcb; /* Command Ring */ + Rcb srcb; /* Send Ring */ + Rcb rsrcb; /* Receive Standard Ring */ + Rcb rjrcb; /* Receive Jumbo Ring */ + Rcb rmrcb; /* Receive Mini Ring */ + Rcb rrrcb; /* Receive Return Ring */ + Host64 epp; /* Event Producer */ + Host64 rrrpp; /* Receive Return Ring Producer */ + Host64 scp; /* Send Consumer */ + Host64 rsp; /* Refresh Stats */ +} Gib; + +/* + * these sizes are all fixed in the card, + * except for Nsr, which has only 3 valid sizes. + */ +enum { /* Host/NIC Interface ring sizes */ + Ner = 256, /* event ring */ + Ncr = 64, /* command ring */ + Nsr = 128, /* send ring: 128, 256 or 512 */ + Nrsr = 512, /* receive standard ring */ + Nrjr = 256, /* receive jumbo ring */ + Nrmr = 1024, /* receive mini ring, optional */ + Nrrr = 2048, /* receive return ring */ +}; + +enum { + NrsrHI = 72, /* Fill-level of Rsr (m.b. < Nrsr) */ + NrsrLO = 54, /* Level at which to top-up ring */ + NrjrHI = 0, /* Fill-level of Rjr (m.b. < Nrjr) */ + NrjrLO = 0, /* Level at which to top-up ring */ + NrmrHI = 0, /* Fill-level of Rmr (m.b. < Nrmr) */ + NrmrLO = 0, /* Level at which to top-up ring */ +}; + +typedef struct Ctlr Ctlr; +struct Ctlr { + int port; + Pcidev* pcidev; + Ctlr* next; + int active; + int id; + + uchar ea[Eaddrlen]; + + int* nic; + Gib* gib; + + Ere* er; + + Lock srlock; + Sbd* sr; + Block** srb; + int nsr; /* currently in send ring */ + + Rbd* rsr; + int nrsr; /* currently in Receive Standard Ring */ + Rbd* rjr; + int nrjr; /* currently in Receive Jumbo Ring */ + Rbd* rmr; + int nrmr; /* currently in Receive Mini Ring */ + Rbd* rrr; + int rrrci; /* Receive Return Ring Consumer Index */ + + int epi[2]; /* Event Producer Index */ + int rrrpi[2]; /* Receive Return Ring Producer Index */ + int sci[3]; /* Send Consumer Index ([2] is host) */ + + int interrupts; /* statistics */ + int mi; + uvlong ticks; + + int coalupdateonly; /* tuning */ + int hardwarecksum; + int rct; /* Receive Coalesce Ticks */ + int sct; /* Send Coalesce Ticks */ + int st; /* Stat Ticks */ + int smcbd; /* Send Max. Coalesced BDs */ + int rmcbd; /* Receive Max. Coalesced BDs */ +}; + +static Ctlr* ctlrhead; +static Ctlr* ctlrtail; + +#define csr32r(c, r) (*((c)->nic+((r)/4))) +#define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v)) + +static void +sethost64(Host64* host64, void* addr) +{ + uvlong uvl; + + uvl = PCIWADDR(addr); + host64->hi = uvl>>32; + host64->lo = uvl & 0xFFFFFFFFL; +} + +static void +ga620command(Ctlr* ctlr, int cmd, int flags, int index) +{ + int cpi; + + cpi = csr32r(ctlr, Cpi); + csr32w(ctlr, Cr+(cpi*4), cmd<<24 | flags<<12 | index); + cpi = NEXT(cpi, Ncr); + csr32w(ctlr, Cpi, cpi); +} + +static void +ga620attach(Ether* ) +{ +} + +static void +waitforlink(Ether *edev) +{ + int i; + + if (edev->mbps == 0) { + print("#l%d: ga620: waiting for link", edev->ctlrno); + /* usually takes about 10 seconds */ + for (i = 0; i < 20 && edev->mbps == 0; i++) { + print("."); + delay(1000); + } + print("\n"); + if (i == 20 && edev->mbps == 0) + edev->mbps = 1; /* buggered */ + } +} + +static void +toringbuf(Ether *ether, Block *bp) +{ + RingBuf *rb = ðer->rb[ether->ri]; + + if (rb->owner == Interface) { + rb->len = BLEN(bp); + memmove(rb->pkt, bp->rp, rb->len); + rb->owner = Host; + ether->ri = NEXT(ether->ri, ether->nrb); + } + /* else no one is expecting packets from the network */ +} + +static Block * +fromringbuf(Ether *ether) +{ + RingBuf *tb = ðer->tb[ether->ti]; + Block *bp = allocb(tb->len); + + if (bp == nil) + panic("fromringbuf: nil allocb return"); + if (bp->wp == nil) + panic("fromringbuf: nil bp->wb"); + memmove(bp->wp, tb->pkt, tb->len); + memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen); + bp->wp += tb->len; + return bp; +} + +static int +_ga620transmit(Ether* edev) +{ + Sbd *sbd; + Block *bp; + Ctlr *ctlr; + RingBuf *tb; + int sci, spi, work; + + /* + * For now there are no smarts here, just empty the + * ring and try to fill it back up. Tuning comes later. + */ + ctlr = edev->ctlr; + waitforlink(edev); + ilock(&ctlr->srlock); + + /* + * Free any completed packets. + * Ctlr->sci[0] is where the NIC has got to consuming the ring. + * Ctlr->sci[2] is where the host has got to tidying up after the + * NIC has done with the packets. + */ + work = 0; + for(sci = ctlr->sci[2]; sci != ctlr->sci[0]; sci = NEXT(sci, Nsr)){ + if(ctlr->srb[sci] == nil) + continue; + freeb(ctlr->srb[sci]); + ctlr->srb[sci] = nil; + work++; + } + ctlr->sci[2] = sci; + + sci = PREV(sci, Nsr); + + tb = &edev->tb[edev->ti]; + for(spi = csr32r(ctlr, Spi); spi != sci && tb->owner == Interface; + spi = NEXT(spi, Nsr)){ + bp = fromringbuf(edev); + + sbd = &ctlr->sr[spi]; + sethost64(&sbd->addr, bp->rp); + sbd->lenflags = BLEN(bp)<<16 |Fend; + + ctlr->srb[spi] = bp; + work++; + + tb->owner = Host; + edev->ti = NEXT(edev->ti, edev->ntb); + tb = &edev->tb[edev->ti]; + } + csr32w(ctlr, Spi, spi); + + iunlock(&ctlr->srlock); + + return work; +} + +static void +ga620transmit(Ether* edev) +{ + _ga620transmit(edev); +} + +static void +ga620replenish(Ctlr* ctlr) +{ + Rbd *rbd; + int rspi; + Block *bp; + + rspi = csr32r(ctlr, Rspi); + while(ctlr->nrsr < NrsrHI){ + if((bp = allocb(ETHERMAXTU+4)) == nil) + break; + rbd = &ctlr->rsr[rspi]; + sethost64(&rbd->addr, bp->rp); + rbd->indexlen = rspi<<16 | (ETHERMAXTU+4); + rbd->flags = 0; + rbd->opaque = bp; + + rspi = NEXT(rspi, Nrsr); + ctlr->nrsr++; + } + csr32w(ctlr, Rspi, rspi); +} + +static void +ga620event(Ether *edev, int eci, int epi) +{ + unsigned event, code; + Ctlr *ctlr; + + ctlr = edev->ctlr; + while(eci != epi){ + event = ctlr->er[eci].event; + code = (event >> 12) & ((1<<12)-1); + switch(event>>24){ + case 0x01: /* firmware operational */ + /* host stack (us) is up. 3rd arg of 2 means down. */ + ga620command(ctlr, 0x01, 0x01, 0x00); + /* + * link negotiation: any speed is okay. + * 3rd arg of 1 selects gigabit only; 2 10/100 only. + */ + ga620command(ctlr, 0x0B, 0x00, 0x00); + print("#l%d: ga620: port %8.8uX: firmware is up\n", + edev->ctlrno, ctlr->port); + break; + case 0x04: /* statistics updated */ + break; + case 0x06: /* link state changed */ + switch (code) { + case 1: + edev->mbps = 1000; + break; + case 2: + print("#l%d: link down\n", edev->ctlrno); + break; + case 3: + edev->mbps = 100; /* it's 10 or 100 */ + break; + } + if (code != 2) + print("#l%d: %dMbps link up\n", + edev->ctlrno, edev->mbps); + break; + case 0x07: /* event error */ + default: + print("#l%d: ga620: er[%d] = %8.8uX\n", edev->ctlrno, + eci, event); + break; + } + eci = NEXT(eci, Ner); + } + csr32w(ctlr, Eci, eci); +} + +static void +ga620receive(Ether* edev) +{ + int len; + Rbd *rbd; + Block *bp; + Ctlr* ctlr; + + ctlr = edev->ctlr; + while(ctlr->rrrci != ctlr->rrrpi[0]){ + rbd = &ctlr->rrr[ctlr->rrrci]; + /* + * Errors are collected in the statistics block so + * no need to tally them here, let ifstat do the work. + */ + len = rbd->indexlen & 0xFFFF; + if(!(rbd->flags & Ferror) && len != 0){ + bp = rbd->opaque; + bp->wp = bp->rp+len; + + toringbuf(edev, bp); + } else + freeb(rbd->opaque); + rbd->opaque = nil; + + if(rbd->flags & Frjr) + ctlr->nrjr--; + else if(rbd->flags & Frmr) + ctlr->nrmr--; + else + ctlr->nrsr--; + + ctlr->rrrci = NEXT(ctlr->rrrci, Nrrr); + } +} + +static void +ga620interrupt(Ureg*, void* arg) +{ + int csr, ie, work; + Ctlr *ctlr; + Ether *edev; + + edev = arg; + ctlr = edev->ctlr; + + if(!(csr32r(ctlr, Mhc) & Is)) + return; + + ctlr->interrupts++; + csr32w(ctlr, Hi, 1); + + ie = 0; + work = 0; + while(ie < 2){ + if(ctlr->rrrci != ctlr->rrrpi[0]){ + ga620receive(edev); + work = 1; + } + + if(_ga620transmit(edev) != 0) + work = 1; + + csr = csr32r(ctlr, Eci); + if(csr != ctlr->epi[0]){ + ga620event(edev, csr, ctlr->epi[0]); + work = 1; + } + + if(ctlr->nrsr <= NrsrLO) + ga620replenish(ctlr); + if(work == 0){ + if(ie == 0) + csr32w(ctlr, Hi, 0); + ie++; + } + work = 0; + } +} + +static void +ga620lmw(Ctlr* ctlr, int addr, int* data, int len) +{ + int i, l, lmw, v; + + /* + * Write to or clear ('data' == nil) 'len' bytes of the NIC + * local memory at address 'addr'. + * The destination address and count should be 32-bit aligned. + */ + v = 0; + while(len > 0){ + /* + * 1) Set the window. The (Lmwsz-1) bits are ignored + * in Wba when accessing through the local memory window; + * 2) Find the minimum of how many bytes still to + * transfer and how many left in this window; + * 3) Create the offset into the local memory window in the + * shared memory space then copy (or zero) the data; + * 4) Bump the counts. + */ + csr32w(ctlr, Wba, addr); + + l = ROUNDUP(addr+1, Lmwsz) - addr; + if(l > len) + l = len; + + lmw = Lmw + (addr & (Lmwsz-1)); + for(i = 0; i < l; i += 4){ + if(data != nil) + v = *data++; + csr32w(ctlr, lmw+i, v); + } + + len -= l; + addr += l; + } +} + +static int +ga620init(Ether* edev) +{ + Ctlr *ctlr; + Host64 host64; + int csr, ea, i, flags; + + ctlr = edev->ctlr; + + /* + * Load the MAC address. + */ + ea = edev->ea[0]<<8 | edev->ea[1]; + csr32w(ctlr, Mac, ea); + ea = edev->ea[2]<<24 | edev->ea[3]<<16 | edev->ea[4]<<8 | edev->ea[5]; + csr32w(ctlr, Mac+4, ea); + + /* + * General Information Block. + */ + ctlr->gib = malloc(sizeof(Gib)); + sethost64(&host64, ctlr->gib); + csr32w(ctlr, Gip, host64.hi); + csr32w(ctlr, Gip+4, host64.lo); + + /* + * Event Ring. + * This is located in host memory. Allocate the ring, + * tell the NIC where it is and initialise the indices. + */ + ctlr->er = malign(sizeof(Ere)*Ner); + sethost64(&ctlr->gib->ercb.addr, ctlr->er); + sethost64(&ctlr->gib->epp, ctlr->epi); + csr32w(ctlr, Eci, 0); + + /* + * Command Ring. + * This is located in the General Communications Region + * and so the value placed in the Rcb is unused, the NIC + * knows where it is. Stick in the value according to + * the datasheet anyway. + * Initialise the ring and indices. + */ + ctlr->gib->crcb.addr.lo = Cr - 0x400; + for(i = 0; i < Ncr*4; i += 4) + csr32w(ctlr, Cr+i, 0); + csr32w(ctlr, Cpi, 0); + csr32w(ctlr, Cci, 0); + + /* + * Send Ring. + * This ring is either in NIC memory at a fixed location depending + * on how big the ring is or it is in host memory. If in NIC + * memory it is accessed via the Local Memory Window; with a send + * ring size of 128 the window covers the whole ring and then need + * only be set once: + * ctlr->sr = (uchar*)ctlr->nic+Lmw; + * ga620lmw(ctlr, Sr, nil, sizeof(Sbd)*Nsr); + * ctlr->gib->srcb.addr.lo = Sr; + * There is nowhere in the Sbd to hold the Block* associated + * with this entry so an external array must be kept. + */ + ctlr->sr = malign(sizeof(Sbd)*Nsr); + sethost64(&ctlr->gib->srcb.addr, ctlr->sr); + if(ctlr->hardwarecksum) + flags = TcpUdpCksum|NoPseudoHdrCksum|HostRing; + else + flags = HostRing; + if(ctlr->coalupdateonly) + flags |= CoalUpdateOnly; + ctlr->gib->srcb.control = Nsr<<16 | flags; + sethost64(&ctlr->gib->scp, ctlr->sci); + csr32w(ctlr, Spi, 0); + ctlr->srb = malloc(sizeof(Block*)*Nsr); + + /* + * Receive Standard Ring. + */ + ctlr->rsr = malign(sizeof(Rbd)*Nrsr); + sethost64(&ctlr->gib->rsrcb.addr, ctlr->rsr); + if(ctlr->hardwarecksum) + flags = TcpUdpCksum|NoPseudoHdrCksum; + else + flags = 0; + ctlr->gib->rsrcb.control = (ETHERMAXTU+4)<<16 | flags; + csr32w(ctlr, Rspi, 0); + + /* + * Jumbo and Mini Rings. Unused for now. + */ + ctlr->gib->rjrcb.control = RingDisabled; + ctlr->gib->rmrcb.control = RingDisabled; + + /* + * Receive Return Ring. + * This is located in host memory. Allocate the ring, + * tell the NIC where it is and initialise the indices. + */ + ctlr->rrr = malign(sizeof(Rbd)*Nrrr); + sethost64(&ctlr->gib->rrrcb.addr, ctlr->rrr); + ctlr->gib->rrrcb.control = Nrrr<<16 | 0; + sethost64(&ctlr->gib->rrrpp, ctlr->rrrpi); + ctlr->rrrci = 0; + + /* + * Refresh Stats Pointer. + * For now just point it at the existing statistics block. + */ + sethost64(&ctlr->gib->rsp, ctlr->gib->statistics); + + /* + * DMA configuration. + * Use the recommended values. + */ + csr32w(ctlr, DMArc, 0x80); + csr32w(ctlr, DMAwc, 0x80); + + /* + * Transmit Buffer Ratio. + * Set to 1/3 of available buffer space (units are 1/64ths) + * if using Jumbo packets, ~64KB otherwise (assume 1MB on NIC). + */ + if(NrjrHI > 0 || Nsr > 128) + csr32w(ctlr, Tbr, 64/3); + else + csr32w(ctlr, Tbr, 4); + + /* + * Tuneable parameters. + * These defaults are based on the tuning hints in the Alteon + * Host/NIC Software Interface Definition and example software. + */ + ctlr->rct = 1 /*100*/; + csr32w(ctlr, Rct, ctlr->rct); + ctlr->sct = 0; + csr32w(ctlr, Sct, ctlr->sct); + ctlr->st = 1000000; + csr32w(ctlr, St, ctlr->st); + ctlr->smcbd = Nsr/4; + csr32w(ctlr, SmcBD, ctlr->smcbd); + ctlr->rmcbd = 4 /*6*/; + csr32w(ctlr, RmcBD, ctlr->rmcbd); + + /* + * Enable DMA Assist Logic. + */ + csr = csr32r(ctlr, DMAas) & ~0x03; + csr32w(ctlr, DMAas, csr|0x01); + + /* + * Link negotiation. + * The bits are set here but the NIC must be given a command + * once it is running to set negotiation in motion. + */ + csr32w(ctlr, Gln, Le|Lean|Lofc|Lfd|L1000MB|Lpref); + csr32w(ctlr, Fln, Le|Lean|Lhd|Lfd|L100MB|L10MB); + + /* + * A unique index for this controller and the maximum packet + * length expected. + * For now only standard packets are expected. + */ + csr32w(ctlr, Ifx, 1); + csr32w(ctlr, IfMTU, ETHERMAXTU+4); + + /* + * Enable Interrupts. + * There are 3 ways to mask interrupts - a bit in the Mhc (which + * is already cleared), the Mi register and the Hi mailbox. + * Writing to the Hi mailbox has the side-effect of clearing the + * PCI interrupt. + */ + csr32w(ctlr, Mi, 0); + csr32w(ctlr, Hi, 0); + + /* + * Start the firmware. + */ + csr32w(ctlr, CPUApc, tigon2FwStartAddr); + csr = csr32r(ctlr, CPUAstate) & ~CPUhalt; + csr32w(ctlr, CPUAstate, csr); + + return 0; +} + +static int +at24c32io(Ctlr* ctlr, char* op, int data) +{ + char *lp, *p; + int i, loop, mlc, r; + + mlc = csr32r(ctlr, Mlc); + + r = 0; + loop = -1; + lp = nil; + for(p = op; *p != '\0'; p++){ + switch(*p){ + default: + return -1; + case ' ': + continue; + case ':': /* start of 8-bit loop */ + if(lp != nil) + return -1; + lp = p; + loop = 7; + continue; + case ';': /* end of 8-bit loop */ + if(lp == nil) + return -1; + loop--; + if(loop >= 0) + p = lp; + else + lp = nil; + continue; + case 'C': /* assert clock */ + mlc |= EEclk; + break; + case 'c': /* deassert clock */ + mlc &= ~EEclk; + break; + case 'D': /* next bit in 'data' byte */ + if(loop < 0) + return -1; + if(data & (1<<loop)) + mlc |= EEdo; + else + mlc &= ~EEdo; + break; + case 'E': /* enable data output */ + mlc |= EEdoe; + break; + case 'e': /* disable data output */ + mlc &= ~EEdoe; + break; + case 'I': /* input bit */ + i = (csr32r(ctlr, Mlc) & EEdi) != 0; + if(loop >= 0) + r |= (i<<loop); + else + r = i; + continue; + case 'O': /* assert data output */ + mlc |= EEdo; + break; + case 'o': /* deassert data output */ + mlc &= ~EEdo; + break; + } + csr32w(ctlr, Mlc, mlc); + microdelay(1); + } + if(loop >= 0) + return -1; + return r; +} + +static int +at24c32r(Ctlr* ctlr, int addr) +{ + int data; + + /* + * Read a byte at address 'addr' from the Atmel AT24C32 + * Serial EEPROM. The 2-wire EEPROM access is controlled + * by 4 bits in Mlc. See the AT24C32 datasheet for + * protocol details. + */ + /* + * Start condition - a high to low transition of data + * with the clock high must precede any other command. + */ + at24c32io(ctlr, "OECoc", 0); + + /* + * Perform a random read at 'addr'. A dummy byte + * write sequence is performed to clock in the device + * and data word addresses (0 and 'addr' respectively). + */ + data = -1; + if(at24c32io(ctlr, "oE :DCc; oeCIc", 0xA0) != 0) + goto stop; + if(at24c32io(ctlr, "oE :DCc; oeCIc", addr>>8) != 0) + goto stop; + if(at24c32io(ctlr, "oE :DCc; oeCIc", addr) != 0) + goto stop; + + /* + * Now send another start condition followed by a + * request to read the device. The EEPROM responds + * by clocking out the data. + */ + at24c32io(ctlr, "OECoc", 0); + if(at24c32io(ctlr, "oE :DCc; oeCIc", 0xA1) != 0) + goto stop; + data = at24c32io(ctlr, ":CIc;", 0xA1); + +stop: + /* + * Stop condition - a low to high transition of data + * with the clock high is a stop condition. After a read + * sequence, the stop command will place the EEPROM in + * a standby power mode. + */ + at24c32io(ctlr, "oECOc", 0); + + return data; +} + +static int +ga620detach(Ctlr* ctlr) +{ + int timeo; + + /* + * Hard reset (don't know which endian so catch both); + * enable for little-endian mode; + * wait for code to be loaded from serial EEPROM or flash; + * make sure CPU A is halted. + */ + csr32w(ctlr, Mhc, Hr<<24 | Hr); + csr32w(ctlr, Mhc, (Eews|Ci)<<24 | Eews|Ci); + + microdelay(1); + for(timeo = 0; timeo < 500000; timeo++){ + if((csr32r(ctlr, CPUAstate) & (CPUhie|CPUrf)) == CPUhie) + break; + microdelay(1); + } + if((csr32r(ctlr, CPUAstate) & (CPUhie|CPUrf)) != CPUhie) + return -1; + csr32w(ctlr, CPUAstate, CPUhalt); + + /* + * After reset, CPU B seems to be stuck in 'CPUrf'. + * Worry about it later. + */ + csr32w(ctlr, CPUBstate, CPUhalt); + + return 0; +} + +static void +ga620shutdown(Ether* ether) +{ +print("ga620shutdown\n"); + ga620detach(ether->ctlr); +} + +static int +ga620reset(Ctlr* ctlr) +{ + int cls, csr, i, r; + + if(ga620detach(ctlr) < 0) + return -1; + + /* + * Tigon 2 PCI NICs have 512KB SRAM per bank. + * Clear out any lingering serial EEPROM state + * bits. + */ + csr = csr32r(ctlr, Mlc) & ~(EEdi|EEdo|EEdoe|EEclk|SRAMmask); + csr32w(ctlr, Mlc, SRAM512|csr); + csr = csr32r(ctlr, Mc); + csr32w(ctlr, Mc, SyncSRAM|csr); + + /* + * Initialise PCI State register. + * If PCI Write-and-Invalidate is enabled set the max write DMA + * value to the host cache-line size (32 on Pentium or later). + */ + csr = csr32r(ctlr, Ps) & (PCI32|PCI66); + csr |= PCIwcmd|PCIrcmd|PCImrm; + if(ctlr->pcidev->pcr & 0x0010){ + cls = pcicfgr8(ctlr->pcidev, PciCLS) * 4; + if(cls != 32) + pcicfgw8(ctlr->pcidev, PciCLS, 32/4); + csr |= PCIwm32; + } + csr32w(ctlr, Ps, csr); + + /* + * Operating Mode. + */ + csr32w(ctlr, Om, Fatal|NoJFrag|BswapDMA|WswapBD); + + /* + * Snarf the MAC address from the serial EEPROM. + */ + for(i = 0; i < Eaddrlen; i++){ + if((r = at24c32r(ctlr, 0x8E+i)) == -1) + return -1; + ctlr->ea[i] = r; + } + + /* + * Load the firmware. + */ + ga620lmw(ctlr, tigon2FwTextAddr, tigon2FwText, tigon2FwTextLen); + ga620lmw(ctlr, tigon2FwRodataAddr, tigon2FwRodata, tigon2FwRodataLen); + ga620lmw(ctlr, tigon2FwDataAddr, tigon2FwData, tigon2FwDataLen); + ga620lmw(ctlr, tigon2FwSbssAddr, nil, tigon2FwSbssLen); + ga620lmw(ctlr, tigon2FwBssAddr, nil, tigon2FwBssLen); + + /* + * we will eventually get events telling us that the firmware is + * up and that the link is up. + */ + return 0; +} + +static void +ga620pci(void) +{ + int port; + Pcidev *p; + Ctlr *ctlr; + + p = nil; + while(p = pcimatch(p, 0, 0)){ + if(p->ccrb != 0x02 || p->ccru != 0) + continue; + + switch(p->did<<16 | p->vid){ + default: + continue; + case 0x620A<<16 | 0x1385: /* Netgear GA620 fiber */ + case 0x630A<<16 | 0x1385: /* Netgear GA620T copper */ + case 0x0001<<16 | 0x12AE: /* Alteon Acenic fiber + * and DEC DEGPA-SA */ + case 0x0002<<16 | 0x12AE: /* Alteon Acenic copper */ + case 0x0009<<16 | 0x10A9: /* SGI Acenic */ + break; + } + + port = upamalloc(p->mem[0].bar & ~0x0F, p->mem[0].size, 0); + if(port == 0){ + print("ga620: can't map %d @ 0x%8.8luX\n", + p->mem[0].size, p->mem[0].bar); + continue; + } + + ctlr = malloc(sizeof(Ctlr)); + ctlr->port = port; + ctlr->pcidev = p; + ctlr->id = p->did<<16 | p->vid; + + ctlr->nic = KADDR(ctlr->port); + if(ga620reset(ctlr)){ + free(ctlr); + continue; + } + + if(ctlrhead != nil) + ctlrtail->next = ctlr; + else + ctlrhead = ctlr; + ctlrtail = ctlr; + } +} + +int +ga620pnp(Ether* edev) +{ + Ctlr *ctlr; + uchar ea[Eaddrlen]; + + if(ctlrhead == nil) + ga620pci(); + + /* + * Any adapter matches if no edev->port is supplied, + * otherwise the ports must match. + */ + for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){ + if(ctlr->active) + continue; + if(edev->port == 0 || edev->port == ctlr->port){ + ctlr->active = 1; + break; + } + } + if(ctlr == nil) + return -1; + + edev->ctlr = ctlr; + edev->port = ctlr->port; + edev->irq = ctlr->pcidev->intl; + edev->tbdf = ctlr->pcidev->tbdf; + + /* + * Check if the adapter's station address is to be overridden. + * If not, read it from the EEPROM and set in ether->ea prior to + * loading the station address in the hardware. + */ + memset(ea, 0, Eaddrlen); + if(memcmp(ea, edev->ea, Eaddrlen) == 0) + memmove(edev->ea, ctlr->ea, Eaddrlen); + + ga620init(edev); /* enables interrupts */ + + /* + * Linkage to the generic ethernet driver. + */ + edev->attach = ga620attach; + edev->transmit = ga620transmit; + edev->interrupt = ga620interrupt; + edev->detach = ga620shutdown; + return 0; +} diff --git a/os/boot/pc/etherga620fw.h b/os/boot/pc/etherga620fw.h new file mode 100644 index 00000000..c30859e7 --- /dev/null +++ b/os/boot/pc/etherga620fw.h @@ -0,0 +1,4858 @@ +/* Generated by genfw.c */ +#define tigon2FwReleaseMajor 0xc +#define tigon2FwReleaseMinor 0x4 +#define tigon2FwReleaseFix 0xb +#define tigon2FwStartAddr 0x00004000 +#define tigon2FwTextAddr 0x00004000 +#define tigon2FwTextLen 0x11bc0 +#define tigon2FwRodataAddr 0x00015bc0 +#define tigon2FwRodataLen 0x10d0 +#define tigon2FwDataAddr 0x00016cc0 +#define tigon2FwDataLen 0x1c0 +#define tigon2FwSbssAddr 0x00016e80 +#define tigon2FwSbssLen 0xcc +#define tigon2FwBssAddr 0x00016f50 +#define tigon2FwBssLen 0x20c0 +static int tigon2FwText[/*(MAX_TEXT_LEN/4) + 1*/] = { +0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c1d0001, 0x8fbd6d20, 0x3a0f021, 0x3c100000, +0x26104000, 0xc0010c0, 0x0, 0xd, +0x3c1d0001, 0x8fbd6d24, 0x3a0f021, 0x3c100000, +0x26104000, 0xc0017e0, 0x0, 0xd, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2000008, +0x0, 0x800172f, 0x3c0a0001, 0x800172f, +0x3c0a0002, 0x800172f, 0x0, 0x8002cac, +0x0, 0x8002c4f, 0x0, 0x800172f, +0x3c0a0004, 0x800328a, 0x0, 0x8001a52, +0x0, 0x800394d, 0x0, 0x80038f4, +0x0, 0x800172f, 0x3c0a0006, 0x80039bb, +0x3c0a0007, 0x800172f, 0x3c0a0008, 0x800172f, +0x3c0a0009, 0x8003a13, 0x0, 0x8002ea6, +0x0, 0x800172f, 0x3c0a000b, 0x800172f, +0x3c0a000c, 0x800172f, 0x3c0a000d, 0x80028fb, +0x0, 0x8002890, 0x0, 0x800172f, +0x3c0a000e, 0x800208c, 0x0, 0x8001964, +0x0, 0x8001a04, 0x0, 0x8003ca6, +0x0, 0x8003c94, 0x0, 0x800172f, +0x0, 0x800191a, 0x0, 0x800172f, +0x0, 0x800172f, 0x3c0a0013, 0x800172f, +0x3c0a0014, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x27bdffe0, +0x3c1cc000, 0xafbf001c, 0xafb00018, 0x8f820140, +0x24030003, 0xaf8300ec, 0x34420004, 0xc002b20, +0xaf820140, 0x3c0100c0, 0xc001763, 0xac203ffc, +0x401821, 0x3c020010, 0x3c010001, 0xac236e9c, +0x10620011, 0x43102b, 0x14400002, 0x3c020020, +0x3c020008, 0x1062000c, 0x24050100, 0x3c060001, +0x8cc66e9c, 0x3c040001, 0x24845c74, 0x3821, +0xafa00010, 0xc002b3b, 0xafa00014, 0x3c020020, +0x3c010001, 0xac226e9c, 0x24020008, 0x3c010001, +0xac226eb4, 0x2402001f, 0x3c010001, 0xac226ec4, +0x24020016, 0x3c010001, 0xac226e98, 0x3c05fffe, +0x34a56f08, 0x3c020001, 0x8c426e9c, 0x3c030002, +0x24639010, 0x3c040001, 0x8c846cc4, 0x431023, +0x14800002, 0x458021, 0x2610fa38, 0x2402f000, +0x2028024, 0xc001785, 0x2002021, 0x2022823, +0x3c040020, 0x821823, 0x651823, 0x247bb000, +0x3c03fffe, 0x3463bf08, 0x363b821, 0x3c0600bf, +0x34c6f000, 0x3c070001, 0x8ce76cc0, 0x3c0300bf, +0x3463e000, 0x852023, 0x3c010001, 0xac246ea8, +0x822023, 0x3c010001, 0xac256e90, 0x52842, +0x3c010001, 0xac226e84, 0x27620ffc, 0x3c010001, +0xac226d20, 0x27621ffc, 0xdb3023, 0x7b1823, +0x3c010001, 0xac246e88, 0x3c010001, 0xac256eac, +0x3c010001, 0xac226d24, 0xaf860150, 0x10e00011, +0xaf830250, 0x3c1d0001, 0x8fbd6ccc, 0x3a0f021, +0xc001749, 0x0, 0x3c020001, 0x8c426cd0, +0x3c030001, 0x8c636cd4, 0x2442fe00, 0x24630200, +0x3c010001, 0xac226cd0, 0x3c010001, 0x10000004, +0xac236cd4, 0x3c1d0001, 0x8fbd6d20, 0x3a0f021, +0x3c020001, 0x8c426cc4, 0x1040000d, 0x26fafa38, +0x3c020001, 0x8c426cd0, 0x3c030001, 0x8c636cd4, +0x3c1a0001, 0x8f5a6cd4, 0x2442fa38, 0x246305c8, +0x3c010001, 0xac226cd0, 0x3c010001, 0xac236cd4, +0x3c020001, 0x8c426cc8, 0x14400003, 0x0, +0x3c010001, 0xac206cd0, 0xc001151, 0x0, +0x8fbf001c, 0x8fb00018, 0x3e00008, 0x27bd0020, +0x3c020001, 0x8c426cd0, 0x3c030001, 0x8c636cd4, +0x27bdff98, 0xafb00048, 0x3c100001, 0x8e1066b8, +0xafb20050, 0x3c120000, 0x26524100, 0xafbf0060, +0xafbe005c, 0xafb50058, 0xafb30054, 0xafb1004c, +0xafa20034, 0xafa30030, 0xafa00010, 0xafa00014, +0x8f860040, 0x3c040001, 0x24845c80, 0x24050200, +0x3c010001, 0xac326e80, 0xc002b3b, 0x2003821, +0x8f830040, 0x3c02f000, 0x621824, 0x3c026000, +0x1062000b, 0xa3a0003f, 0x240e0001, 0x3c040001, +0x24845c88, 0xa3ae003f, 0xafa00010, 0xafa00014, +0x8f860040, 0x24050300, 0xc002b3b, 0x2003821, +0x8f820240, 0x3c030001, 0x431025, 0xaf820240, +0xaf800048, 0x8f820048, 0x14400005, 0x0, +0xaf800048, 0x8f820048, 0x10400004, 0x0, +0xaf800048, 0x10000003, 0x2e02021, 0xaf80004c, +0x2e02021, 0x3c050001, 0xc002ba8, 0x34a540f8, +0x3402021, 0xc002ba8, 0x240505c8, 0x3c020001, +0x8c426ea8, 0x3c0d0001, 0x8dad6e88, 0x3c030001, +0x8c636e84, 0x3c080001, 0x8d086e90, 0x3c090001, +0x8d296eac, 0x3c0a0001, 0x8d4a6eb4, 0x3c0b0001, +0x8d6b6ec4, 0x3c0c0001, 0x8d8c6e98, 0x3c040001, +0x24845c94, 0x24050400, 0xaf42013c, 0x8f42013c, +0x24060001, 0x24070001, 0xaf400000, 0xaf4d0138, +0xaf430144, 0xaf480148, 0xaf49014c, 0xaf4a0150, +0xaf4b0154, 0xaf4c0158, 0x2442ff80, 0xaf420140, +0x24020001, 0xafa20010, 0xc002b3b, 0xafa00014, +0x8f420138, 0xafa20010, 0x8f42013c, 0xafa20014, +0x8f460144, 0x8f470148, 0x3c040001, 0x24845ca0, +0xc002b3b, 0x24050500, 0xafb70010, 0xafba0014, +0x8f46014c, 0x8f470150, 0x3c040001, 0x24845cac, +0xc002b3b, 0x24050600, 0x3c020001, 0x8c426e9c, +0x3603821, 0x3c060002, 0x24c69010, 0x2448ffff, +0x1061824, 0xe81024, 0x43102b, 0x10400006, +0x24050900, 0x3c040001, 0x24845cb8, 0xafa80010, +0xc002b3b, 0xafa00014, 0x8f82000c, 0xafa20010, +0x8f82003c, 0xafa20014, 0x8f860000, 0x8f870004, +0x3c040001, 0x24845cc4, 0xc002b3b, 0x24051000, +0x8c020220, 0x8c030224, 0x8c060218, 0x8c07021c, +0x3c040001, 0x24845ccc, 0x24051100, 0xafa20010, +0xc002b3b, 0xafa30014, 0xaf800054, 0xaf80011c, +0x8c020218, 0x30420002, 0x10400009, 0x0, +0x8c020220, 0x3c030002, 0x34630004, 0x431025, +0xaf42000c, 0x8c02021c, 0x10000008, 0x34420004, +0x8c020220, 0x3c030002, 0x34630006, 0x431025, +0xaf42000c, 0x8c02021c, 0x34420006, 0xaf420014, +0x8c020218, 0x30420010, 0x1040000a, 0x0, +0x8c02021c, 0x34420004, 0xaf420010, 0x8c020220, +0x3c03000a, 0x34630004, 0x431025, 0x10000009, +0xaf420008, 0x8c020220, 0x3c03000a, 0x34630006, +0x431025, 0xaf420008, 0x8c02021c, 0x34420006, +0xaf420010, 0x24020001, 0xaf8200a0, 0xaf8200b0, +0x8f830054, 0x8f820054, 0xaf8000d0, 0xaf8000c0, +0x10000002, 0x24630064, 0x8f820054, 0x621023, +0x2c420065, 0x1440fffc, 0x0, 0x8c040208, +0x8c05020c, 0x26e20028, 0xaee20020, 0x24020490, +0xaee20010, 0xaee40008, 0xaee5000c, 0x26e40008, +0x8c820000, 0x8c830004, 0xaf820090, 0xaf830094, +0x8c820018, 0xaf8200b4, 0x9482000a, 0xaf82009c, +0x8f420014, 0xaf8200b0, 0x8f8200b0, 0x30420004, +0x1440fffd, 0x0, 0x8f8200b0, 0x3c03ef00, +0x431024, 0x10400021, 0x0, 0x8f8200b4, +0xafa20010, 0x8f820090, 0x8f830094, 0x3c040001, +0x24845cd4, 0xafa30014, 0x8f8600b0, 0x8f87009c, +0x3c050001, 0xc002b3b, 0x34a5200d, 0x3c040001, +0x24845ce0, 0x240203c0, 0xafa20010, 0xafa00014, +0x8f860144, 0x3c070001, 0x24e75ce8, 0xc002b3b, +0x3405dead, 0x8f82011c, 0x34420002, 0xaf82011c, +0x8f820220, 0x34420004, 0xaf820220, 0x8f820140, +0x3c030001, 0x431025, 0xaf820140, 0x96e20472, +0x96e60452, 0x96e70462, 0xafa20010, 0x96e20482, +0x3c040001, 0x24845d14, 0x24051200, 0xc002b3b, +0xafa20014, 0x96f00452, 0x32020001, 0x10400002, +0xb021, 0x24160001, 0x32020002, 0x54400001, +0x36d60002, 0x32020008, 0x54400001, 0x36d60004, +0x32020010, 0x54400001, 0x36d60008, 0x32020020, +0x54400001, 0x36d60010, 0x32020040, 0x54400001, +0x36d60020, 0x32020080, 0x54400001, 0x36d60040, +0x96e60482, 0x30c20200, 0x54400001, 0x36d64000, +0x96e30472, 0x30620200, 0x10400003, 0x30620100, +0x10000003, 0x36d62000, 0x54400001, 0x36d61000, +0x96f00462, 0x32c24000, 0x14400004, 0x3207009b, +0x30c2009b, 0x14e20007, 0x240e0001, 0x32c22000, +0x1440000d, 0x32020001, 0x3062009b, 0x10e20009, +0x240e0001, 0x3c040001, 0x24845d20, 0x24051300, +0x2003821, 0xa3ae003f, 0xafa30010, 0xc002b3b, +0xafa00014, 0x32020001, 0x54400001, 0x36d60080, +0x32020002, 0x54400001, 0x36d60100, 0x32020008, +0x54400001, 0x36d60200, 0x32020010, 0x54400001, +0x36d60400, 0x32020080, 0x54400001, 0x36d60800, +0x8c020218, 0x30420200, 0x10400002, 0x3c020008, +0x2c2b025, 0x8c020218, 0x30420800, 0x10400002, +0x3c020080, 0x2c2b025, 0x8c020218, 0x30420400, +0x10400002, 0x3c020100, 0x2c2b025, 0x8c020218, +0x30420100, 0x10400002, 0x3c020200, 0x2c2b025, +0x8c020218, 0x30420080, 0x10400002, 0x3c020400, +0x2c2b025, 0x8c020218, 0x30422000, 0x10400002, +0x3c020010, 0x2c2b025, 0x8c020218, 0x30424000, +0x10400002, 0x3c020020, 0x2c2b025, 0x8c020218, +0x30421000, 0x10400002, 0x3c020040, 0x2c2b025, +0x8ee20498, 0x8ee3049c, 0xaf420160, 0xaf430164, +0x8ee204a0, 0x8ee304a4, 0xaf420168, 0xaf43016c, +0x8ee204a8, 0x8ee304ac, 0xaf420170, 0xaf430174, +0x8ee20428, 0x8ee3042c, 0xaf420178, 0xaf43017c, +0x8ee20448, 0x8ee3044c, 0xaf420180, 0xaf430184, +0x8ee20458, 0x8ee3045c, 0xaf420188, 0xaf43018c, +0x8ee20468, 0x8ee3046c, 0xaf420190, 0xaf430194, +0x8ee20478, 0x8ee3047c, 0xaf420198, 0xaf43019c, +0x8ee20488, 0x8ee3048c, 0xaf4201a0, 0xaf4301a4, +0x8ee204b0, 0x8ee304b4, 0x24040080, 0xaf4201a8, +0xaf4301ac, 0xc002ba8, 0x24050080, 0x8c02025c, +0x27440224, 0xaf4201f0, 0x8c020260, 0x24050200, +0x24060008, 0xc002bbf, 0xaf4201f8, 0x3c043b9a, +0x3484ca00, 0x3821, 0x24020006, 0x24030002, +0xaf4201f4, 0x240203e8, 0xaf430204, 0xaf430200, +0xaf4401fc, 0xaf420294, 0x24020001, 0xaf430290, +0xaf42029c, 0x3c030001, 0x671821, 0x90636cd8, +0x3471021, 0x24e70001, 0xa043022c, 0x2ce2000f, +0x1440fff8, 0x3471821, 0x24e70001, 0x3c080001, +0x350840f8, 0x8f820040, 0x3c040001, 0x24845d2c, +0x24051400, 0x21702, 0x24420030, 0xa062022c, +0x3471021, 0xa040022c, 0x8c070218, 0x2c03021, +0x240205c8, 0xafa20010, 0xc002b3b, 0xafa80014, +0x3c040001, 0x24845d38, 0x3c050000, 0x24a55c80, +0x24060010, 0x27b10030, 0x2203821, 0x27b30034, +0xc0017a3, 0xafb30010, 0x3c030001, 0x8c636cc8, +0x1060000a, 0x408021, 0x8fa30030, 0x2405ff00, +0x8fa20034, 0x246400ff, 0x852024, 0x831823, +0x431023, 0xafa20034, 0xafa40030, 0x3c040001, +0x24845d44, 0x3c050000, 0x24a54100, 0x24060108, +0x2203821, 0xc0017a3, 0xafb30010, 0x409021, +0x32c20003, 0x3c010001, 0xac326e80, 0x10400045, +0x2203821, 0x8f820050, 0x3c030010, 0x431024, +0x10400016, 0x0, 0x8c020218, 0x30420040, +0x1040000f, 0x24020001, 0x8f820050, 0x8c030218, +0x240e0001, 0x3c040001, 0x24845d50, 0xa3ae003f, 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+0x3c02fffe, 0x3442ffff, 0xc23024, 0xaf840200, +0xaf860220, 0x8f820220, 0x34420002, 0xaf820220, +0x121140, 0x3c010002, 0x220821, 0xac308ff0, +0x8fbf002c, 0x8fb20028, 0x8fb10024, 0x8fb00020, +0x3e00008, 0x27bd0030, 0x0, 0x1821, +0x308400ff, 0x2405ffdf, 0x2406ffbf, 0x641007, +0x30420001, 0x10400004, 0x0, 0x8f820044, +0x10000003, 0x34420040, 0x8f820044, 0x461024, +0xaf820044, 0x8f820044, 0x34420020, 0xaf820044, +0x8f820044, 0x451024, 0xaf820044, 0x24630001, +0x28620008, 0x5440ffee, 0x641007, 0x3e00008, +0x0, 0x2c820008, 0x1040001b, 0x0, +0x2405ffdf, 0x2406ffbf, 0x41880, 0x3c020001, +0x24426e60, 0x621821, 0x24640004, 0x90620000, +0x10400004, 0x0, 0x8f820044, 0x10000003, +0x34420040, 0x8f820044, 0x461024, 0xaf820044, +0x8f820044, 0x34420020, 0xaf820044, 0x8f820044, +0x451024, 0xaf820044, 0x24630001, 0x64102b, +0x1440ffee, 0x0, 0x3e00008, 0x0, +0x0, 0x0, 0x0, 0x8f8400c4, +0x8f8600e0, 0x8f8700e4, 0x2402fff8, 0xc22824, +0x10e5001a, 0x27623ff8, 0x14e20002, 0x24e80008, +0x27683000, 0x55050004, 0x8d0a0000, 0x30c20004, +0x14400012, 0x805021, 0x8ce90000, 0x8f42013c, +0x1494823, 0x49182b, 0x94eb0006, 0x10600002, +0x25630050, 0x494821, 0x123182b, 0x50400003, +0x8f4201fc, 0x3e00008, 0xe01021, 0xaf8800e8, +0x24420001, 0xaf4201fc, 0xaf8800e4, 0x3e00008, +0x1021, 0x3e00008, 0x0, 0x8f8300e4, +0x27623ff8, 0x10620004, 0x24620008, 0xaf8200e8, +0x3e00008, 0xaf8200e4, 0x27623000, 0xaf8200e8, +0x3e00008, 0xaf8200e4, 0x3e00008, 0x0, +0x0, 0x0, 0x0, 0x8f880120, +0x27624fe0, 0x8f830128, 0x15020002, 0x25090020, +0x27694800, 0x11230012, 0x8fa20010, 0xad040000, +0xad050004, 0xad060008, 0xa507000e, 0x8fa30014, +0xad020018, 0x8fa20018, 0xad03001c, 0x25030016, +0xad020010, 0xad030014, 0xaf890120, 0x8f4300fc, +0x24020001, 0x2463ffff, 0x3e00008, 0xaf4300fc, +0x8f430324, 0x1021, 0x24630001, 0x3e00008, +0xaf430324, 0x3e00008, 0x0, 0x8f880100, +0x276247e0, 0x8f830108, 0x15020002, 0x25090020, +0x27694000, 0x1123000f, 0x8fa20010, 0xad040000, +0xad050004, 0xad060008, 0xa507000e, 0x8fa30014, +0xad020018, 0x8fa20018, 0xad03001c, 0x25030016, +0xad020010, 0xad030014, 0xaf890100, 0x3e00008, +0x24020001, 0x8f430328, 0x1021, 0x24630001, +0x3e00008, 0xaf430328, 0x3e00008, 0x0, +0x0, 0x0, 0x0, 0x0 }; +static int tigon2FwRodata[/*(MAX_RODATA_LEN/4) + 1*/] = { +0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f6677, 0x6d61696e, 0x2e632c76, 0x20312e31, +0x2e322e34, 0x35203139, 0x39392f30, 0x312f3234, +0x2030303a, 0x31303a35, 0x35207368, 0x75616e67, +0x20457870, 0x20240000, 0x65767452, 0x6e674600, +0x51657674, 0x46000000, 0x51657674, 0x505f4600, +0x4d657674, 0x526e6746, 0x0, 0x4d516576, +0x74460000, 0x4d516576, 0x505f4600, 0x5173436f, +0x6e495f46, 0x0, 0x5173436f, 0x6e734600, +0x51725072, 0x6f644600, 0x6261644d, 0x656d537a, +0x0, 0x68775665, 0x72000000, 0x62616448, +0x77566572, 0x0, 0x2a2a4441, 0x574e5f41, +0x0, 0x74785278, 0x4266537a, 0x0, +0x62664174, 0x6e4d726b, 0x0, 0x7265645a, +0x6f6e6531, 0x0, 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+0x51725072, 0x6f644600, 0x3f48636d, 0x644d6278, +0x0, 0x3f636d64, 0x48737453, 0x0, +0x3f636d64, 0x4d634d64, 0x0, 0x3f636d64, +0x50726f6d, 0x0, 0x3f636d64, 0x4c696e6b, +0x0, 0x3f636d64, 0x45727200, 0x86ac, +0x8e5c, 0x8e5c, 0x8de4, 0x8b78, +0x8e30, 0x8e5c, 0x8790, 0x8800, +0x8990, 0x8a68, 0x8a34, 0x8e5c, +0x8870, 0x8b24, 0x8e5c, 0x8b34, +0x87b4, 0x8824, 0x0, 0x0, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f6d63, 0x6173742e, 0x632c7620, 0x312e312e, +0x322e3820, 0x31393938, 0x2f31322f, 0x30382030, +0x323a3336, 0x3a333620, 0x73687561, 0x6e672045, +0x78702024, 0x0, 0x65767452, 0x6e674600, +0x51657674, 0x46000000, 0x51657674, 0x505f4600, +0x4d657674, 0x526e6746, 0x0, 0x4d516576, +0x74460000, 0x4d516576, 0x505f4600, 0x5173436f, +0x6e495f46, 0x0, 0x5173436f, 0x6e734600, +0x51725072, 0x6f644600, 0x6164644d, 0x63447570, +0x0, 0x6164644d, 0x6346756c, 0x0, +0x64656c4d, 0x634e6f45, 0x0, 0x0, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f646d, 0x612e632c, 0x7620312e, 0x312e322e, +0x32342031, 0x3939382f, 0x31322f32, 0x31203030, +0x3a33333a, 0x30392073, 0x6875616e, 0x67204578, +0x70202400, 0x65767452, 0x6e674600, 0x51657674, +0x46000000, 0x51657674, 0x505f4600, 0x4d657674, +0x526e6746, 0x0, 0x4d516576, 0x74460000, +0x4d516576, 0x505f4600, 0x5173436f, 0x6e495f46, +0x0, 0x5173436f, 0x6e734600, 0x51725072, +0x6f644600, 0x7377446d, 0x614f6666, 0x0, +0x31446d61, 0x4f6e0000, 0x7377446d, 0x614f6e00, +0x2372446d, 0x6141544e, 0x0, 0x72446d61, +0x41544e30, 0x0, 0x72446d61, 0x41544e31, +0x0, 0x72446d61, 0x34476200, 0x2a50414e, +0x49432a00, 0x2e2e2f2e, 0x2e2f2e2e, 0x2f2e2e2f, +0x2e2e2f73, 0x72632f6e, 0x69632f66, 0x77322f63, +0x6f6d6d6f, 0x6e2f646d, 0x612e6300, 0x2377446d, +0x6141544e, 0x0, 0x77446d61, 0x41544e30, +0x0, 0x77446d61, 0x41544e31, 0x0, +0x77446d61, 0x34476200, 0x0, 0x0, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f7472, 0x6163652e, 0x632c7620, 0x312e312e, +0x322e3520, 0x31393938, 0x2f30392f, 0x33302031, +0x383a3530, 0x3a323820, 0x73687561, 0x6e672045, +0x78702024, 0x0, 0x0, 0x0, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f6461, 0x74612e63, 0x2c762031, 0x2e312e32, +0x2e313220, 0x31393939, 0x2f30312f, 0x32302031, +0x393a3439, 0x3a353120, 0x73687561, 0x6e672045, +0x78702024, 0x0, 0x46575f56, 0x45525349, +0x4f4e3a20, 0x23312046, 0x72692041, 0x70722037, +0x2031373a, 0x35373a35, 0x32205044, 0x54203230, +0x30300000, 0x46575f43, 0x4f4d5049, 0x4c455f54, +0x494d453a, 0x2031373a, 0x35373a35, 0x32000000, +0x46575f43, 0x4f4d5049, 0x4c455f42, 0x593a2064, +0x65767263, 0x73000000, 0x46575f43, 0x4f4d5049, +0x4c455f48, 0x4f53543a, 0x20636f6d, 0x70757465, +0x0, 0x46575f43, 0x4f4d5049, 0x4c455f44, +0x4f4d4149, 0x4e3a2065, 0x6e672e61, 0x6374656f, +0x6e2e636f, 0x6d000000, 0x46575f43, 0x4f4d5049, +0x4c45523a, 0x20676363, 0x20766572, 0x73696f6e, +0x20322e37, 0x2e320000, 0x0, 0x12041100, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f6d65, 0x6d2e632c, 0x7620312e, 0x312e322e, +0x35203139, 0x39382f30, 0x392f3330, 0x2031383a, +0x35303a30, 0x38207368, 0x75616e67, 0x20457870, +0x20240000, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f7365, 0x6e642e63, 0x2c762031, 0x2e312e32, +0x2e343420, 0x31393938, 0x2f31322f, 0x32312030, +0x303a3333, 0x3a313820, 0x73687561, 0x6e672045, +0x78702024, 0x0, 0x65767452, 0x6e674600, +0x51657674, 0x46000000, 0x51657674, 0x505f4600, +0x4d657674, 0x526e6746, 0x0, 0x4d516576, +0x74460000, 0x4d516576, 0x505f4600, 0x5173436f, +0x6e495f46, 0x0, 0x5173436f, 0x6e734600, +0x51725072, 0x6f644600, 0x69736e74, 0x54637055, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f7265, 0x63762e63, 0x2c762031, 0x2e312e32, +0x2e353320, 0x31393939, 0x2f30312f, 0x31362030, +0x323a3535, 0x3a343320, 0x73687561, 0x6e672045, +0x78702024, 0x0, 0x65767452, 0x6e674600, +0x51657674, 0x46000000, 0x51657674, 0x505f4600, +0x4d657674, 0x526e6746, 0x0, 0x4d516576, +0x74460000, 0x4d516576, 0x505f4600, 0x5173436f, +0x6e495f46, 0x0, 0x5173436f, 0x6e734600, +0x51725072, 0x6f644600, 0x724d6163, 0x43686b30, +0x0, 0x72784672, 0x6d324c67, 0x0, +0x72784e6f, 0x53744264, 0x0, 0x72784e6f, +0x4d694264, 0x0, 0x72784e6f, 0x4a6d4264, +0x0, 0x7278436b, 0x446d6146, 0x0, +0x72785144, 0x6d457846, 0x0, 0x72785144, +0x6d614600, 0x72785144, 0x4c426446, 0x0, +0x72785144, 0x6d426446, 0x0, 0x72784372, +0x63506164, 0x0, 0x72536d51, 0x446d6146, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f6d61, 0x632e632c, 0x7620312e, 0x312e322e, +0x32322031, 0x3939382f, 0x31322f30, 0x38203032, +0x3a33363a, 0x33302073, 0x6875616e, 0x67204578, +0x70202400, 0x65767452, 0x6e674600, 0x51657674, +0x46000000, 0x51657674, 0x505f4600, 0x4d657674, +0x526e6746, 0x0, 0x4d516576, 0x74460000, +0x4d516576, 0x505f4600, 0x5173436f, 0x6e495f46, +0x0, 0x5173436f, 0x6e734600, 0x51725072, +0x6f644600, 0x6d616354, 0x68726573, 0x0, +0x23744d61, 0x6341544e, 0x0, 0x23724d61, +0x6341544e, 0x0, 0x72656d41, 0x73737274, +0x0, 0x6c696e6b, 0x444f574e, 0x0, +0x6c696e6b, 0x55500000, 0x0, 0x0, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x77322f63, 0x6f6d6d6f, +0x6e2f636b, 0x73756d2e, 0x632c7620, 0x312e312e, +0x322e3920, 0x31393939, 0x2f30312f, 0x31342030, +0x303a3033, 0x3a343820, 0x73687561, 0x6e672045, +0x78702024, 0x0, 0x65767452, 0x6e674600, +0x51657674, 0x46000000, 0x51657674, 0x505f4600, +0x4d657674, 0x526e6746, 0x0, 0x4d516576, +0x74460000, 0x4d516576, 0x505f4600, 0x5173436f, +0x6e495f46, 0x0, 0x5173436f, 0x6e734600, +0x51725072, 0x6f644600, 0x0, 0x0, +0x0, 0x50726f62, 0x65506879, 0x0, +0x6c6e6b41, 0x53535254, 0x0, 0x109a4, +0x10a1c, 0x10a50, 0x10a7c, 0x11050, +0x10aa8, 0x10b10, 0x111fc, 0x10dc0, +0x10c68, 0x10c80, 0x10cc4, 0x10cec, +0x10d0c, 0x10d34, 0x111fc, 0x10dc0, +0x10df8, 0x10e10, 0x10e40, 0x10e68, +0x10e88, 0x10eb0, 0x0, 0x10fdc, +0x11008, 0x1102c, 0x111fc, 0x11050, +0x11078, 0x11108, 0x0, 0x0, +0x0, 0x1186c, 0x1193c, 0x11a14, +0x11ae4, 0x11b40, 0x11c1c, 0x11c44, +0x11d20, 0x11d48, 0x11ef0, 0x11f18, +0x120c0, 0x122b8, 0x1254c, 0x12460, +0x1254c, 0x12578, 0x120e8, 0x12290, +0x7273745f, 0x676d6969, 0x0, 0x12608, +0x12640, 0x12728, 0x13374, 0x133b4, +0x133cc, 0x7365746c, 0x6f6f7000, 0x0, +0x0, 0x13bbc, 0x13bfc, 0x13c8c, +0x13cd0, 0x13d34, 0x13dc0, 0x13df4, +0x13e7c, 0x13f14, 0x13fe4, 0x14024, +0x140a8, 0x140cc, 0x141dc, 0x646f4261, +0x73655067, 0x0, 0x0, 0x0, +0x0, 0x73746d61, 0x634c4e4b, 0x0, +0x6765746d, 0x636c6e6b, 0x0, 0x14ed8, +0x14ed8, 0x14b8c, 0x14bd8, 0x14c24, +0x14ed8, 0x7365746d, 0x61636163, 0x74000000, +0x0, 0x0 }; +static int tigon2FwData[/*(MAX_DATA_LEN/4) + 1*/] = { +0x1, +0x1, 0x1, 0xc001fc, 0x3ffc, +0xc00000, 0x416c7465, 0x6f6e2041, 0x63654e49, +0x43205600, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x416c7465, +0x6f6e2041, 0x63654e49, 0x43205600, 0x42424242, +0x0, 0x0, 0x0, 0x1ffffc, +0x1fff7c, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x60cf00, +0x60, 0xcf000000, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x3, 0x0, +0x1, 0x0, 0x0, 0x0, +0x1, 0x0, 0x1, 0x0, +0x0, 0x0, 0x0, 0x1, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x1000000, 0x21000000, +0x12000140, 0x0, 0x0, 0x20000000, +0x120000a0, 0x0, 0x12000060, 0x12000180, +0x120001e0, 0x0, 0x0, 0x0, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2, +0x0, 0x0, 0x30001, 0x1, +0x30201, 0x0, 0x0, 0x1010101, +0x1010100, 0x10100, 0x1010001, 0x10001, +0x1000101, 0x101, 0x0, 0x0 }; diff --git a/os/boot/pc/etherif.h b/os/boot/pc/etherif.h index 522fd9b0..f4a6482c 100644 --- a/os/boot/pc/etherif.h +++ b/os/boot/pc/etherif.h @@ -17,7 +17,7 @@ typedef struct Ether Ether; struct Ether { ISAConf; /* hardware info */ int ctlrno; - int state; + int state; /* 0: unfound, 1: found, 2: attaching */ int tbdf; void (*attach)(Ether*); /* filled in by reset routine */ @@ -36,7 +36,8 @@ struct Ether { ushort th; /* first transmit buffer belonging to host */ ushort ti; /* first transmit buffer belonging to card */ - int tbusy; /* transmitter is busy */ + int tbusy; /* transmitter is busy */ + int mbps; /* zero means link down */ }; extern void etherrloop(Ether*, Etherpkt*, long); diff --git a/os/boot/pc/etherigbe.c b/os/boot/pc/etherigbe.c index f65ea7ba..f0200855 100644 --- a/os/boot/pc/etherigbe.c +++ b/os/boot/pc/etherigbe.c @@ -1,6 +1,6 @@ /* * bootstrap driver for - * Intel RS-82543GC Gigabit Ethernet Controller + * Intel RS-82543GC Gigabit Ethernet PCI Controllers * as found on the Intel PRO/1000[FT] Server Adapter. * The older non-[FT] cards use the 82542 (LSI L2A1157) chip; no attempt * is made to handle the older chip although it should be possible. @@ -31,17 +31,21 @@ #include "ethermii.h" enum { + Debug = 0, /* mostly for X60 debugging */ +}; +enum { i82542 = (0x1000<<16)|0x8086, i82543gc = (0x1004<<16)|0x8086, i82544ei = (0x1008<<16)|0x8086, - i82547ei = (0x1019<<16)|0x8086, i82540em = (0x100E<<16)|0x8086, + i82546eb = (0x1010<<16)|0x8086, + i82547ei = (0x1019<<16)|0x8086, i82540eplp = (0x101E<<16)|0x8086, i82547gi = (0x1075<<16)|0x8086, i82541gi = (0x1076<<16)|0x8086, + i82541gi2 = (0x1077<<16)|0x8086, i82546gb = (0x1079<<16)|0x8086, i82541pi = (0x107c<<16)|0x8086, - i82546eb = (0x1010<<16)|0x8086, }; /* compatibility with cpu kernels */ @@ -139,10 +143,15 @@ enum { /* Ctrl */ Vme = 0x40000000, /* VLAN Mode Enable */ }; +/* + * can't find Tckok nor Rbcok in any Intel docs, + * but even 82543gc docs define Lanid. + */ enum { /* Status */ Lu = 0x00000002, /* Link Up */ - Tckok = 0x00000004, /* Transmit clock is running */ - Rbcok = 0x00000008, /* Receive clock is running */ + Lanid = 0x0000000C, /* mask for Lan ID. (function id) */ +// Tckok = 0x00000004, /* Transmit clock is running */ +// Rbcok = 0x00000008, /* Receive clock is running */ Txoff = 0x00000010, /* Transmission Paused */ Tbimode = 0x00000020, /* TBI Mode Indication */ SpeedMASK = 0x000000C0, @@ -169,7 +178,9 @@ enum { /* Eecd */ Do = 0x00000008, /* Data Output from the EEPROM */ Areq = 0x00000040, /* EEPROM Access Request */ Agnt = 0x00000080, /* EEPROM Access Grant */ + Eepresent = 0x00000100, /* EEPROM Present */ Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */ + Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */ Spi = 0x00002000, /* EEPROM is SPI not Microwire */ }; @@ -385,8 +396,8 @@ enum { /* Tdesc status */ }; enum { - Nrdesc = 128, /* multiple of 8 */ - Ntdesc = 128, /* multiple of 8 */ + Nrdesc = 32, /* multiple of 8 */ + Ntdesc = 8, /* multiple of 8 */ }; typedef struct Ctlr Ctlr; @@ -724,7 +735,7 @@ igbeinterrupt(Ureg*, void* arg) */ if(icr & (Rxseq|Lsc)){ /* - * More here... + * should be more here... */ } @@ -845,10 +856,11 @@ igbeinit(Ether* edev) case i82540em: case i82540eplp: case i82541gi: + case i82541gi2: + case i82541pi: case i82546gb: case i82546eb: case i82547gi: - case i82541pi: csr32w(ctlr, Radv, 64); break; } @@ -887,6 +899,7 @@ igbeinit(Ether* edev) case i82540em: case i82540eplp: case i82541gi: + case i82541gi2: case i82541pi: case i82546gb: case i82546eb: @@ -925,10 +938,11 @@ igbeinit(Ether* edev) case i82540em: case i82540eplp: case i82547gi: + case i82541pi: case i82546gb: case i82546eb: case i82541gi: - case i82541pi: + case i82541gi2: r = csr32r(ctlr, Txdctl); r &= ~WthreshMASK; r |= Gran|(4<<WthreshSHIFT); @@ -1157,6 +1171,7 @@ igbemii(Ctlr* ctlr) case i82540eplp: case i82547gi: case i82541gi: + case i82541gi2: case i82541pi: case i82546gb: case i82546eb: @@ -1178,7 +1193,10 @@ igbemii(Ctlr* ctlr) ctlr->mii = nil; return -1; } - print("oui %X phyno %d\n", phy->oui, phy->phyno); + if (Debug) + print("oui %X phyno %d\n", phy->oui, phy->phyno); + else + USED(phy); /* * 8254X-specific PHY registers not in 802.3: @@ -1190,6 +1208,7 @@ igbemii(Ctlr* ctlr) switch(ctlr->id){ case i82547gi: case i82541gi: + case i82541gi2: case i82541pi: case i82546gb: case i82546eb: @@ -1200,13 +1219,13 @@ igbemii(Ctlr* ctlr) r |= 0x0060; /* auto-crossover all speeds */ r |= 0x0002; /* polarity reversal enabled */ miimiw(ctlr->mii, 16, r); - + r = miimir(ctlr->mii, 20); r |= 0x0070; /* +25MHz clock */ r &= ~0x0F00; r |= 0x0100; /* 1x downshift */ miimiw(ctlr->mii, 20, r); - + miireset(ctlr->mii); break; } @@ -1288,7 +1307,7 @@ at93c46io(Ctlr* ctlr, char* op, int data) break; } csr32w(ctlr, Eecd, eecd); - microdelay(1); + microdelay(50); } if(loop >= 0) return -1; @@ -1307,12 +1326,10 @@ at93c46r(Ctlr* ctlr) print("igbe: SPI EEPROM access not implemented\n"); return 0; } - if(eecd & Eesz256) + if(eecd & (Eeszaddr|Eesz256)) bits = 8; else bits = 6; - snprint(rop, sizeof(rop), "S :%dDCc;", bits+3); - sum = 0; switch(ctlr->id){ @@ -1322,6 +1339,7 @@ at93c46r(Ctlr* ctlr) case i82540em: case i82540eplp: case i82541gi: + case i82541gi2: case i82541pi: case i82547gi: case i82546gb: @@ -1339,6 +1357,7 @@ at93c46r(Ctlr* ctlr) } break; } + snprint(rop, sizeof(rop), "S :%dDCc;", bits+3); for(addr = 0; addr < 0x40; addr++){ /* @@ -1355,8 +1374,14 @@ at93c46r(Ctlr* ctlr) at93c46io(ctlr, "sic", 0); ctlr->eeprom[addr] = data; sum += data; + if (Debug) { + if(addr && ((addr & 0x07) == 0)) + print("\n"); + print(" %4.4ux", data); + } } - + if (Debug) + print("\n"); release: if(areq) csr32w(ctlr, Eecd, eecd & ~Areq); @@ -1377,7 +1402,7 @@ detach(Ctlr *ctlr) csr32w(ctlr, Rctl, 0); csr32w(ctlr, Tctl, 0); - delay(10); + delay(20); csr32w(ctlr, Ctrl, Devrst); /* apparently needed on multi-GHz processors to avoid infinite loops */ @@ -1396,6 +1421,7 @@ detach(Ctlr *ctlr) case i82540em: case i82540eplp: case i82541gi: + case i82541gi2: case i82541pi: case i82547gi: case i82546gb: @@ -1448,12 +1474,18 @@ igbereset(Ctlr* ctlr) * There are 16 addresses. The first should be the MAC address. * The others are cleared and not marked valid (MS bit of Rah). */ - if ((ctlr->id == i82546gb || ctlr->id == i82546eb) && BUSFNO(ctlr->pcidev->tbdf) == 1) - ctlr->eeprom[Ea+2] += 0x100; // second interface + if ((ctlr->id == i82546gb || ctlr->id == i82546eb) && + BUSFNO(ctlr->pcidev->tbdf) == 1) + ctlr->eeprom[Ea+2] += 0x100; /* second interface */ for(i = Ea; i < Eaddrlen/2; i++){ - ctlr->ra[2*i] = ctlr->eeprom[i]; + ctlr->ra[2*i] = ctlr->eeprom[i]; ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8; } + /* lan id seems to vary on 82543gc; don't use it */ + if (ctlr->id != i82543gc) { + r = (csr32r(ctlr, Status) & Lanid) >> 2; + ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */ + } r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0]; csr32w(ctlr, Ral, r); r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4]; @@ -1480,7 +1512,7 @@ igbereset(Ctlr* ctlr) txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd); ctrl = csr32r(ctlr, Ctrl); ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd); - + if(ctlr->eeprom[Icw1] & 0x0400){ ctrl |= Fd; txcw |= TxcwFd; @@ -1502,7 +1534,7 @@ igbereset(Ctlr* ctlr) ctrl |= Ips; ctrl |= swdpio<<SwdpiohiSHIFT; csr32w(ctlr, Ctrlext, ctrl); - + if(ctlr->eeprom[Icw2] & 0x0800) txcw |= TxcwAne; pause = (ctlr->eeprom[Icw2] & 0x3000)>>12; @@ -1539,7 +1571,7 @@ igbereset(Ctlr* ctlr) ilock(&ctlr->imlock); csr32w(ctlr, Imc, ~0); - ctlr->im = Lsc; + ctlr->im = 0; /* was = Lsc, which hangs some controllers */ csr32w(ctlr, Ims, ctlr->im); iunlock(&ctlr->imlock); @@ -1583,6 +1615,7 @@ igbepci(void) case i82540eplp: case i82547gi: case i82541gi: + case i82541gi2: case i82541pi: case i82546gb: case i82546eb: @@ -1633,12 +1666,14 @@ igbepci(void) ctlr->id = (p->did<<16)|p->vid; ctlr->cls = cls*4; ctlr->nic = KADDR(ctlr->port); -print("status0 %8.8uX\n", csr32r(ctlr, Status)); + if (Debug) + print("status0 %8.8uX\n", csr32r(ctlr, Status)); if(igbereset(ctlr)){ free(ctlr); continue; } -print("status1 %8.8uX\n", csr32r(ctlr, Status)); + if (Debug) + print("status1 %8.8uX\n", csr32r(ctlr, Status)); pcisetbme(p); if(ctlrhead != nil) diff --git a/os/boot/pc/etherrhine.c b/os/boot/pc/etherrhine.c index b4d37bf5..2a582c72 100644 --- a/os/boot/pc/etherrhine.c +++ b/os/boot/pc/etherrhine.c @@ -1,4 +1,4 @@ - /* +/* Via Rhine driver, written for VT6102. Uses the ethermii to control PHY. @@ -7,7 +7,7 @@ (almost) copy-free by using (possibly) two descriptors (if it allows arbitrary tx lengths, which it should..): first for alignment and second for rest of the frame. Rx-part should be worth doing. -*/ + */ #include "u.h" #include "lib.h" #include "mem.h" @@ -18,267 +18,228 @@ typedef struct QLock { int r; } QLock; #define qlock(i) while(0) #define qunlock(i) while(0) -#define coherence() #define iprint print #include "etherif.h" #include "ethermii.h" -typedef struct Desc Desc; -typedef struct Ctlr Ctlr; - enum { Ntxd = 4, Nrxd = 4, Nwait = 50, - Ntxstats = 9, - Nrxstats = 8, BIGSTR = 8192, }; +typedef struct Desc Desc; +typedef struct Ctlr Ctlr; + struct Desc { - ulong stat; - ulong size; - ulong addr; - ulong next; - char *buf; - ulong pad[3]; + ulong stat; + ulong size; + ulong addr; + ulong next; + char *buf; + ulong pad[3]; }; struct Ctlr { - Pcidev *pci; - int attached; - int txused; - int txhead; - int txtail; - int rxtail; - ulong port; + Pcidev *pci; + int attached; + int txused; + int txhead; + int txtail; + int rxtail; + ulong port; - Mii mii; + Mii mii; - ulong txstats[Ntxstats]; - ulong rxstats[Nrxstats]; + Desc *txd; /* wants to be aligned on 16-byte boundary */ + Desc *rxd; - Desc *txd; /* wants to be aligned on 16-byte boundary */ - Desc *rxd; - - QLock attachlck; - Lock tlock; + QLock attachlck; + Lock tlock; }; #define ior8(c, r) (inb((c)->port+(r))) +#define iow8(c, r, b) (outb((c)->port+(r), (int)(b))) #define ior16(c, r) (ins((c)->port+(r))) #define ior32(c, r) (inl((c)->port+(r))) -#define iow8(c, r, b) (outb((c)->port+(r), (int)(b))) #define iow16(c, r, w) (outs((c)->port+(r), (ushort)(w))) #define iow32(c, r, l) (outl((c)->port+(r), (ulong)(l))) +/* names used everywhere else */ +#define csr8r ior8 +#define csr8w iow8 +#define csr16r ior16 +#define csr16w iow16 +#define csr32r ior32 +#define csr32w iow32 + enum Regs { - Eaddr = 0x0, - Rcr = 0x6, - Tcr = 0x7, - Cr = 0x8, - Isr = 0xc, - Imr = 0xe, - McastAddr = 0x10, - RxdAddr = 0x18, - TxdAddr = 0x1C, - Bcr = 0x6e, - RhineMiiPhy = 0x6C, - RhineMiiSr = 0x6D, - RhineMiiCr = 0x70, - RhineMiiAddr = 0x71, - RhineMiiData = 0x72, - Eecsr = 0x74, - ConfigB = 0x79, - ConfigD = 0x7B, - MiscCr = 0x80, - HwSticky = 0x83, - MiscIsr = 0x84, - MiscImr = 0x86, - WolCrSet = 0xA0, - WolCfgSet = 0xA1, - WolCgSet = 0xA3, - WolCrClr = 0xA4, - PwrCfgClr = 0xA5, - WolCgClr = 0xA7, + Eaddr = 0x0, + Rcr = 0x6, + Tcr = 0x7, + Cr = 0x8, + Isr = 0xc, + Imr = 0xe, + McastAddr = 0x10, + RxdAddr = 0x18, + TxdAddr = 0x1C, + Bcr0 = 0x6E, /* Bus Control */ + Bcr1 = 0x6F, + RhineMiiPhy = 0x6C, + RhineMiiSr = 0x6D, + RhineMiiCr = 0x70, + RhineMiiAddr = 0x71, + RhineMiiData = 0x72, + Eecsr = 0x74, + ConfigB = 0x79, + ConfigD = 0x7B, + MiscCr = 0x80, + HwSticky = 0x83, + MiscIsr = 0x84, + MiscImr = 0x86, + WolCrSet = 0xA0, + WolCfgSet = 0xA1, + WolCgSet = 0xA3, + WolCrClr = 0xA4, + PwrCfgClr = 0xA5, + WolCgClr = 0xA7, }; -enum Rcrbits { - RxErrX = 1<<0, - RxSmall = 1<<1, - RxMcast = 1<<2, - RxBcast = 1<<3, - RxProm = 1<<4, - RxFifo64 = 0<<5, RxFifo32 = 1<<5, RxFifo128 = 2<<5, RxFifo256 = 3<<5, - RxFifo512 = 4<<5, RxFifo768 = 5<<5, RxFifo1024 = 6<<5, - RxFifoStoreForward = 7<<5, +enum { /* Rcr */ + Sep = 0x01, /* Accept Error Packets */ + Ar = 0x02, /* Accept Small Packets */ + Am = 0x04, /* Accept Multicast */ + Ab = 0x08, /* Accept Broadcast */ + RxBcast = Ab, + Prom = 0x10, /* Accept Physical Address Packets */ + RxProm = Prom, + RrftMASK = 0xE0, /* Receive FIFO Threshold */ + RrftSHIFT = 5, + Rrft64 = 0<<RrftSHIFT, + Rrft32 = 1<<RrftSHIFT, + Rrft128 = 2<<RrftSHIFT, + Rrft256 = 3<<RrftSHIFT, + Rrft512 = 4<<RrftSHIFT, + Rrft768 = 5<<RrftSHIFT, + Rrft1024 = 6<<RrftSHIFT, + RrftSAF = 7<<RrftSHIFT, }; -enum Tcrbits { - TxLoopback0 = 1<<1, - TxLoopback1 = 1<<2, - TxBackoff = 1<<3, - TxFifo128 = 0<<5, TxFifo256 = 1<<5, TxFifo512 = 2<<5, TxFifo1024 = 3<<5, - TxFifoStoreForward = 7<<5, +enum { /* Tcr */ + Lb0 = 0x02, /* Loopback Mode */ + Lb1 = 0x04, + Ofset = 0x08, /* Back-off Priority Selection */ + RtsfMASK = 0xE0, /* Transmit FIFO Threshold */ + RtsfSHIFT = 5, + Rtsf128 = 0<<RtsfSHIFT, + Rtsf256 = 1<<RtsfSHIFT, + Rtsf512 = 2<<RtsfSHIFT, + Rtsf1024 = 3<<RtsfSHIFT, + RtsfSAF = 7<<RtsfSHIFT, }; enum Crbits { - Init = 1<<0, - Start = 1<<1, - Stop = 1<<2, - RxOn = 1<<3, - TxOn = 1<<4, - Tdmd = 1<<5, - Rdmd = 1<<6, - EarlyRx = 1<<8, - Reserved0 = 1<<9, - FullDuplex = 1<<10, - NoAutoPoll = 1<<11, - Reserved1 = 1<<12, - Tdmd1 = 1<<13, - Rdmd1 = 1<<14, - Reset = 1<<15, + Init = 1<<0, + Start = 1<<1, + Stop = 1<<2, + RxOn = 1<<3, + TxOn = 1<<4, + Tdmd = 1<<5, + Rdmd = 1<<6, + EarlyRx = 1<<8, + Reserved0 = 1<<9, + FullDuplex = 1<<10, + NoAutoPoll = 1<<11, + Reserved1 = 1<<12, + Tdmd1 = 1<<13, + Rdmd1 = 1<<14, + Reset = 1<<15, }; enum Isrbits { - RxOk = 1<<0, - TxOk = 1<<1, - RxErr = 1<<2, - TxErr = 1<<3, - TxBufUdf = 1<<4, - RxBufLinkErr = 1<<5, - BusErr = 1<<6, - CrcOvf = 1<<7, - EarlyRxInt = 1<<8, - TxFifoUdf = 1<<9, - RxFifoOvf = 1<<10, - TxPktRace = 1<<11, - NoRxbuf = 1<<12, - TxCollision = 1<<13, - PortCh = 1<<14, - GPInt = 1<<15 + RxOk = 1<<0, + TxOk = 1<<1, + RxErr = 1<<2, + TxErr = 1<<3, + TxBufUdf = 1<<4, + RxBufLinkErr = 1<<5, + BusErr = 1<<6, + CrcOvf = 1<<7, + EarlyRxInt = 1<<8, + TxFifoUdf = 1<<9, + RxFifoOvf = 1<<10, + TxPktRace = 1<<11, + NoRxbuf = 1<<12, + TxCollision = 1<<13, + PortCh = 1<<14, + GPInt = 1<<15, }; -enum Bcrbits { - Dma32 = 0<<0, Dma64 = 1<<0, Dma128 = 2<<0, - Dma256 = 3<<0, Dma512 = 4<<0, Dma1024 = 5<<0, - DmaStoreForward = 7<<0, - DupRxFifo0 = 1<<3, DupRxFifo1 = 1<<4, DupRxFifo2 = 1<<5, - ExtraLed = 1<<6, - MediumSelect = 1<<7, - PollTimer0 = 1<<8, PollTimer1 = 1<<9, PollTimer2 = 1<<10, - DupTxFifo0 = 1<<11, DupTxFifo1 = 1<<12, DupTxFifo2 = 1<<13, +enum { /* Bcr0 */ + DmaMASK = 0x07, /* DMA Length */ + DmaSHIFT = 0, + Dma32 = 0<<DmaSHIFT, + Dma64 = 1<<DmaSHIFT, + Dma128 = 2<<DmaSHIFT, + Dma256 = 3<<DmaSHIFT, + Dma512 = 4<<DmaSHIFT, + Dma1024 = 5<<DmaSHIFT, + DmaSAF = 7<<DmaSHIFT, + CrftMASK = 0x38, /* Rx FIFO Threshold */ + CrftSHIFT = 3, + Crft64 = 1<<CrftSHIFT, + Crft128 = 2<<CrftSHIFT, + Crft256 = 3<<CrftSHIFT, + Crft512 = 4<<CrftSHIFT, + Crft1024 = 5<<CrftSHIFT, + CrftSAF = 7<<CrftSHIFT, + Extled = 0x40, /* Extra LED Support Control */ + Med2 = 0x80, /* Medium Select Control */ }; -enum Eecsrbits { - EeAutoLoad = 1<<5, +enum { /* Bcr1 */ + PotMASK = 0x07, /* Polling Timer Interval */ + PotSHIFT = 0, + CtftMASK = 0x38, /* Tx FIFO Threshold */ + CtftSHIFT = 3, + Ctft64 = 1<<CtftSHIFT, + Ctft128 = 2<<CtftSHIFT, + Ctft256 = 3<<CtftSHIFT, + Ctft512 = 4<<CtftSHIFT, + Ctft1024 = 5<<CtftSHIFT, + CtftSAF = 7<<CtftSHIFT, }; -enum MiscCrbits { - Timer0Enable= 1<<0, - Timer0Suspend = 1<<1, - HalfDuplexFlowControl = 1<<2, - FullDuplexFlowControl = 1<<3, - Timer1Enable = 1<<8, - ForceSoftReset = 1<<14, -}; -enum HwStickybits { - StickyDS0 = 1<<0, - StickyDS1 = 1<<1, - WOLEna = 1<<2, - WOLStat = 1<<3, -}; - -enum WolCgbits { - PmeOvr = 1<<7, +enum Eecsrbits { + EeAutoLoad = 1<<5, }; enum Descbits { - OwnNic = 1<<31, /* stat */ - TxAbort = 1<<8, /* stat */ - TxError = 1<<15, /* stat */ - RxChainbuf = 1<<10, /* stat */ - RxChainStart = 1<<9, /* stat */ - RxChainEnd = 1<<8, /* stat */ - Chainbuf = 1<<15, /* size rx & tx*/ - TxDisableCrc = 1<<16, /* size */ - TxChainStart = 1<<21, /* size */ - TxChainEnd = 1<<22, /* size */ - TxInt = 1<<23, /* size */ -}; - -enum ConfigDbits { - BackoffOptional = 1<<0, - BackoffAMD = 1<<1, - BackoffDEC = 1<<2, - BackoffRandom = 1<<3, - PmccTestMode = 1<<4, - PciReadlineCap = 1<<5, - DiagMode = 1<<6, - MmioEnable = 1<<7, -}; - -enum ConfigBbits { - LatencyTimer = 1<<0, - WriteWaitState = 1<<1, - ReadWaitState = 1<<2, - RxArbit = 1<<3, - TxArbit = 1<<4, - NoMemReadline = 1<<5, - NoParity = 1<<6, - NoTxQueuing = 1<<7, + OwnNic = 1<<31, /* stat */ + TxAbort = 1<<8, /* stat */ + TxError = 1<<15, /* stat */ + RxChainbuf = 1<<10, /* stat */ + RxChainStart = 1<<9, /* stat */ + RxChainEnd = 1<<8, /* stat */ + Chainbuf = 1<<15, /* size rx & tx*/ + TxDisableCrc = 1<<16, /* size */ + TxChainStart = 1<<21, /* size */ + TxChainEnd = 1<<22, /* size */ + TxInt = 1<<23, /* size */ }; enum RhineMiiCrbits { - Mdc = 1<<0, - Mdi = 1<<1, - Mdo = 1<<2, - Mdout = 1<<3, - Mdpm = 1<<4, - Wcmd = 1<<5, - Rcmd = 1<<6, - Mauto = 1<<7, -}; - -enum RhineMiiSrbits { - Speed10M = 1<<0, - LinkFail = 1<<1, - PhyError = 1<<3, - DefaultPhy = 1<<4, - ResetPhy = 1<<7, -}; - -enum RhineMiiAddrbits { - Mdone = 1<<5, - Msrcen = 1<<6, - Midle = 1<<7, -}; - -static char * -txstatnames[Ntxstats] = { - "aborts (excess collisions)", - "out of window collisions", - "carrier sense losses", - "fifo underflows", - "invalid descriptor format or underflows", - "system errors", - "reserved", - "transmit errors", - "collisions", -}; - -static char * -rxstatnames[Nrxstats] = { - "receiver errors", - "crc errors", - "frame alignment errors", - "fifo overflows", - "long packets", - "run packets", - "system errors", - "buffer underflows", + Mdc = 1<<0, + Mdi = 1<<1, + Mdo = 1<<2, + Mdout = 1<<3, + Mdpm = 1<<4, + Wcmd = 1<<5, + Rcmd = 1<<6, + Mauto = 1<<7, }; static void @@ -289,7 +250,7 @@ attach(Ether *edev) Mii *mi; MiiPhy *phy; int i, s; - + ctlr = edev->ctlr; qlock(&ctlr->attachlck); if (ctlr->attached == 0) { @@ -321,14 +282,15 @@ attach(Ether *edev) s = splhi(); iow32(ctlr, TxdAddr, PCIWADDR(&txd[0])); iow32(ctlr, RxdAddr, PCIWADDR(&rxd[0])); - iow16(ctlr, Cr, (phy->fd ? FullDuplex : 0) | NoAutoPoll | TxOn | RxOn | Start | Rdmd); + iow16(ctlr, Cr, (phy->fd? FullDuplex: 0) | NoAutoPoll | TxOn | + RxOn | Start | Rdmd); iow16(ctlr, Isr, 0xFFFF); iow16(ctlr, Imr, 0xFFFF); iow8(ctlr, MiscIsr, 0xFF); iow8(ctlr, MiscImr, ~(3<<5)); splx(s); + ctlr->attached = 1; } - ctlr->attached++; qunlock(&ctlr->attachlck); } @@ -341,23 +303,21 @@ txstart(Ether *edev) RingBuf *tb; ctlr = edev->ctlr; - txd = ctlr->txd; i = ctlr->txhead; - txused = ctlr->txused; n = 0; - while (txused < Ntxd) { + for (txused = ctlr->txused; txused < Ntxd; txused++) { tb = &edev->tb[edev->ti]; if(tb->owner != Interface) break; td = &txd[i]; memmove(td->buf, tb->pkt, tb->len); - td->size = tb->len | TxChainStart | TxChainEnd | TxInt; /* could reduce number of ints here */ + /* could reduce number of intrs here */ + td->size = tb->len | TxChainStart | TxChainEnd | TxInt; coherence(); td->stat = OwnNic; i = (i + 1) % Ntxd; - txused++; n++; tb->owner = Host; @@ -374,6 +334,7 @@ static void transmit(Ether *edev) { Ctlr *ctlr; + ctlr = edev->ctlr; ilock(&ctlr->tlock); txstart(edev); @@ -385,27 +346,18 @@ txcomplete(Ether *edev) { Ctlr *ctlr; Desc *txd, *td; - int i, txused, j; + int i, txused; ulong stat; ctlr = edev->ctlr; txd = ctlr->txd; - txused = ctlr->txused; i = ctlr->txtail; - while (txused > 0) { + for (txused = ctlr->txused; txused > 0; txused--) { td = &txd[i]; stat = td->stat; - if (stat & OwnNic) break; - - ctlr->txstats[Ntxstats-1] += stat & 0xF; - for (j = 0; j < Ntxstats-1; ++j) - if (stat & (1<<(j+8))) - ctlr->txstats[j]++; - i = (i + 1) % Ntxd; - txused--; } ctlr->txused = txused; ctlr->txtail = i; @@ -423,14 +375,15 @@ interrupt(Ureg *, void *arg) ushort isr, misr; ulong stat; Desc *rxd, *rd; - int i, n, j, size; + int i, n, size; edev = (Ether*)arg; ctlr = edev->ctlr; iow16(ctlr, Imr, 0); isr = ior16(ctlr, Isr); iow16(ctlr, Isr, 0xFFFF); - misr = ior16(ctlr, MiscIsr) & ~(3<<5); /* don't care about used defined ints */ + /* don't care about used defined intrs */ + misr = ior16(ctlr, MiscIsr) & ~(3<<5); if (isr & RxOk) { rxd = ctlr->rxd; @@ -440,14 +393,9 @@ interrupt(Ureg *, void *arg) while ((rxd[i].stat & OwnNic) == 0) { rd = &rxd[i]; stat = rd->stat; - for (j = 0; j < Nrxstats; ++j) - if (stat & (1<<j)) - ctlr->rxstats[j]++; - if (stat & 0xFF) iprint("rx: %lux\n", stat & 0xFF); - - size = ((rd->stat>>16) & 2047) - 4; + size = ((rd->stat>>16) & (2048-1)) - 4; rb = &edev->rb[edev->ri]; if(rb->owner == Interface){ @@ -473,24 +421,11 @@ interrupt(Ureg *, void *arg) isr &= ~TxOk; } if (isr | misr) - iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n", isr, misr); - + iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n", + isr, misr); iow16(ctlr, Imr, 0xFFFF); } -static void -promiscuous(void *arg, int enable) -{ - Ether *edev; - Ctlr *ctlr; - - edev = arg; - ctlr = edev->ctlr; - ilock(&ctlr->tlock); - iow8(ctlr, Rcr, ior8(ctlr, Rcr) | (enable ? RxProm : RxBcast)); - iunlock(&ctlr->tlock); -} - static int miiread(Mii *mii, int phy, int reg) { @@ -498,7 +433,7 @@ miiread(Mii *mii, int phy, int reg) int n; ctlr = mii->ctlr; - + n = Nwait; while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd)) microdelay(1); @@ -516,9 +451,7 @@ miiread(Mii *mii, int phy, int reg) if (n == Nwait) iprint("etherrhine: miiread: timeout\n"); - n = ior16(ctlr, RhineMiiData); - - return n; + return ior16(ctlr, RhineMiiData); } static int @@ -553,17 +486,50 @@ miiwrite(Mii *mii, int phy, int reg, int data) static void reset(Ctlr* ctlr) { - int i; - - iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop); - iow16(ctlr, Cr, ior16(ctlr, Cr) | Reset); + int r, timeo; + + /* + * Soft reset the controller. + */ + csr16w(ctlr, Cr, Stop); + csr16w(ctlr, Cr, Stop|Reset); + for(timeo = 0; timeo < 10000; timeo++){ + if(!(csr16r(ctlr, Cr) & Reset)) + break; + microdelay(1); + } + if(timeo >= 1000) + return; - for (i = 0; i < Nwait; ++i) { - if ((ior16(ctlr, Cr) & Reset) == 0) - return; - delay(5); + /* + * Load the MAC address into the PAR[01] + * registers. + */ + r = csr8r(ctlr, Eecsr); + csr8w(ctlr, Eecsr, EeAutoLoad|r); + for(timeo = 0; timeo < 100; timeo++){ + if(!(csr8r(ctlr, Cr) & EeAutoLoad)) + break; + microdelay(1); } - iprint("etherrhine: reset timeout\n"); + if(timeo >= 100) + return; + + /* + * Configure DMA and Rx/Tx thresholds. + * If the Rx/Tx threshold bits in Bcr[01] are 0 then + * the thresholds are determined by Rcr/Tcr. + */ + r = csr8r(ctlr, Bcr0) & ~(CrftMASK|DmaMASK); + csr8w(ctlr, Bcr0, r|Crft64|Dma64); + r = csr8r(ctlr, Bcr1) & ~CtftMASK; + csr8w(ctlr, Bcr1, r|Ctft64); + + r = csr8r(ctlr, Rcr) & ~(RrftMASK|Prom|Ar|Sep); + csr8w(ctlr, Rcr, r|Ab|Am); + + r = csr8r(ctlr, Tcr) & ~(RtsfMASK|Ofset|Lb1|Lb0); + csr8w(ctlr, Tcr, r); } static void @@ -579,11 +545,9 @@ init(Ether *edev) int i; ctlr = edev->ctlr; - ilock(&ctlr->tlock); pcisetbme(ctlr->pci); - reset(ctlr); iow8(ctlr, Eecsr, ior8(ctlr, Eecsr) | EeAutoLoad); @@ -592,7 +556,7 @@ init(Ether *edev) break; delay(5); } - if (i == Nwait) + if (i >= Nwait) iprint("etherrhine: eeprom autoload timeout\n"); for (i = 0; i < Eaddrlen; ++i) @@ -603,6 +567,7 @@ init(Ether *edev) ctlr->mii.ctlr = ctlr; if(mii(&ctlr->mii, ~0) == 0 || ctlr->mii.curphy == nil){ + iunlock(&ctlr->tlock); iprint("etherrhine: init mii failure\n"); return; } @@ -610,7 +575,6 @@ init(Ether *edev) if (ctlr->mii.phy[i]) if (ctlr->mii.phy[i]->oui != 0xFFFFF) ctlr->mii.curphy = ctlr->mii.phy[i]; - miistatus(&ctlr->mii); iow16(ctlr, Imr, 0); @@ -626,12 +590,22 @@ rhinematch(ulong) int nfound = 0; Pcidev *p = nil; - while (p = pcimatch(p, 0x1106, 0)) - if (p->did == 0x3065) + while(p = pcimatch(p, 0x1106, 0)){ + if(p->ccrb != Pcibcnet || p->ccru != Pciscether) + continue; + switch((p->did<<16)|p->vid){ + default: + continue; + case (0x3053<<16)|0x1106: /* Rhine III vt6105m (Soekris) */ + case (0x3065<<16)|0x1106: /* Rhine II */ + case (0x3106<<16)|0x1106: /* Rhine III */ if (++nfound > nrhines) { nrhines++; - break; + return p; } + break; + } + } return p; } @@ -642,6 +616,8 @@ rhinepnp(Ether *edev) Ctlr *ctlr; ulong port; + if (edev->attach) + return 0; p = rhinematch(edev->port); if (p == nil) return -1; @@ -655,7 +631,7 @@ rhinepnp(Ether *edev) memset(ctlr, 0, sizeof(Ctlr)); ctlr->txd = xspanalloc(sizeof(Desc) * Ntxd, 16, 0); ctlr->rxd = xspanalloc(sizeof(Desc) * Nrxd, 16, 0); - + ctlr->pci = p; ctlr->port = port; @@ -666,7 +642,6 @@ rhinepnp(Ether *edev) init(edev); - edev->attach = attach; edev->transmit = transmit; edev->interrupt = interrupt; @@ -674,3 +649,9 @@ rhinepnp(Ether *edev) return 0; } + +int +vt6102pnp(Ether *edev) +{ + return rhinepnp(edev); +} diff --git a/os/boot/pc/fns.h b/os/boot/pc/fns.h index 794fe592..d0481833 100644 --- a/os/boot/pc/fns.h +++ b/os/boot/pc/fns.h @@ -4,6 +4,12 @@ Alarm* alarm(int, void (*)(Alarm*), void*); void alarminit(void); Block* allocb(int); void apminit(void); +int biosboot(int dev, char *file, Boot *b); +void* biosgetfspart(int i, char *name, int chatty); +void biosinitdev(int i, char *name); +int biosinit(void); +void biosprintbootdevs(int dev); +void biosprintdevs(int i); int bootpboot(int, char*, Boot*); int bootpass(Boot*, void*, int); void cancel(Alarm*); @@ -15,6 +21,7 @@ int cistrncmp(char*, char*, int); void changeconf(char*, ...); void checkalarms(void); void clockinit(void); +#define coherence() mb386() void consdrain(void); void consinit(char*, char*); void consputs(char*, int); @@ -53,11 +60,14 @@ ulong inl(int); void insb(int, void*, int); void inss(int, void*, int); void insl(int, void*, int); +#define ioalloc(addr, len, align, name) (addr) +#define iofree(addr) void iunlock(Lock*); int isaconfig(char*, int, ISAConf*); void kbdinit(void); void kbdchar(int); void machinit(void); +void mb386(void); void meminit(ulong); void microdelay(int); void mmuinit(void); @@ -71,19 +81,29 @@ void outsb(int, void*, int); void outss(int, void*, int); void outsl(int, void*, int); void panic(char*, ...); +ulong pcibarsize(Pcidev*, int); int pcicfgr8(Pcidev*, int); int pcicfgr16(Pcidev*, int); int pcicfgr32(Pcidev*, int); void pcicfgw8(Pcidev*, int, int); void pcicfgw16(Pcidev*, int, int); void pcicfgw32(Pcidev*, int, int); +void pciclrbme(Pcidev*); +void pciclrioe(Pcidev*); +void pciclrmwi(Pcidev*); +int pcigetpms(Pcidev*); void pcihinv(Pcidev*); Pcidev* pcimatch(Pcidev*, int, int); uchar pciintl(Pcidev *); uchar pciipin(Pcidev *, uchar); void pcireset(void); void pcisetbme(Pcidev*); -int pcmcistuple(int, int, void*, int); +void pcisetioe(Pcidev*); +void pcisetmwi(Pcidev*); +int pcisetpms(Pcidev*, int); +void pcmcisread(PCMslot*); +int pcmcistuple(int, int, int, void*, int); +PCMmap* pcmmap(int, ulong, int, int); int pcmspecial(char*, ISAConf*); void pcmspecialclose(int); void pcmunmap(int, PCMmap*); diff --git a/os/boot/pc/io.h b/os/boot/pc/io.h index 67219ddd..6e7564f4 100644 --- a/os/boot/pc/io.h +++ b/os/boot/pc/io.h @@ -85,6 +85,54 @@ enum { /* type 0 and type 1 pre-defined header */ PciINTP = 0x3D, /* interrupt pin */ }; +/* ccrb (base class code) values; controller types */ +enum { + Pcibcpci1 = 0, /* pci 1.0; no class codes defined */ + Pcibcstore = 1, /* mass storage */ + Pcibcnet = 2, /* network */ + Pcibcdisp = 3, /* display */ + Pcibcmmedia = 4, /* multimedia */ + Pcibcmem = 5, /* memory */ + Pcibcbridge = 6, /* bridge */ + Pcibccomm = 7, /* simple comms (e.g., serial) */ + Pcibcbasesys = 8, /* base system */ + Pcibcinput = 9, /* input */ + Pcibcdock = 0xa, /* docking stations */ + Pcibcproc = 0xb, /* processors */ + Pcibcserial = 0xc, /* serial bus (e.g., USB) */ + Pcibcwireless = 0xd, /* wireless */ + Pcibcintell = 0xe, /* intelligent i/o */ + Pcibcsatcom = 0xf, /* satellite comms */ + Pcibccrypto = 0x10, /* encryption/decryption */ + Pcibcdacq = 0x11, /* data acquisition & signal proc. */ +}; + +/* ccru (sub-class code) values; common cases only */ +enum { + /* mass storage */ + Pciscscsi = 0, /* SCSI */ + Pciscide = 1, /* IDE (ATA) */ + + /* network */ + Pciscether = 0, /* Ethernet */ + + /* display */ + Pciscvga = 0, /* VGA */ + Pciscxga = 1, /* XGA */ + Pcisc3d = 2, /* 3D */ + + /* bridges */ + Pcischostpci = 0, /* host/pci */ + Pciscpcicpci = 1, /* pci/pci */ + + /* simple comms */ + Pciscserial = 0, /* 16450, etc. */ + Pciscmultiser = 1, /* multiport serial */ + + /* serial bus */ + Pciscusb = 3, /* USB */ +}; + enum { /* type 0 pre-defined header */ PciBAR2 = 0x18, PciBAR3 = 0x1C, @@ -133,7 +181,7 @@ enum { /* type 2 pre-defined header */ PciCBILR0 = 0x30, /* I/O limit */ PciCBIBR1 = 0x34, /* I/O base */ PciCBILR1 = 0x38, /* I/O limit */ - PciCBBCTL = 0x3E, /* Bridhe control */ + PciCBBCTL = 0x3E, /* Bridge control */ PciCBSVID = 0x40, /* subsystem vendor ID */ PciCBSID = 0x42, /* subsystem ID */ PciCBLMBAR = 0x44, /* legacy mode base address */ @@ -153,10 +201,14 @@ typedef struct Pcidev { ushort vid; /* vendor ID */ ushort did; /* device ID */ + ushort pcr; + uchar rid; uchar ccrp; uchar ccru; uchar ccrb; + uchar cls; + uchar ltr; struct { ulong bar; /* base address */ @@ -170,14 +222,15 @@ typedef struct Pcidev { uchar intl; /* interrupt line */ Pcidev* list; - Pcidev* bridge; /* down a bus */ Pcidev* link; /* next device on this bno */ + + Pcidev* bridge; /* down a bus */ struct { ulong bar; int size; } ioa, mema; - ulong pcr; + int pmrb; /* power management register block */ }; #define PCIWINDOW 0 @@ -188,6 +241,9 @@ typedef struct Pcidev { /* * PCMCIA support code. */ +typedef struct PCMslot PCMslot; +typedef struct PCMconftab PCMconftab; + /* * Map between ISA memory space and PCMCIA card memory space. */ @@ -199,3 +255,63 @@ struct PCMmap { int attr; /* attribute memory */ int ref; }; + +/* configuration table entry */ +struct PCMconftab +{ + int index; + ushort irqs; /* legal irqs */ + uchar irqtype; + uchar bit16; /* true for 16 bit access */ + struct { + ulong start; + ulong len; + } io[16]; + int nio; + uchar vpp1; + uchar vpp2; + uchar memwait; + ulong maxwait; + ulong readywait; + ulong otherwait; +}; + +/* a card slot */ +struct PCMslot +{ + Lock; + int ref; + + void *cp; /* controller for this slot */ + long memlen; /* memory length */ + uchar base; /* index register base */ + uchar slotno; /* slot number */ + + /* status */ + uchar special; /* in use for a special device */ + uchar already; /* already inited */ + uchar occupied; + uchar battery; + uchar wrprot; + uchar powered; + uchar configed; + uchar enabled; + uchar busy; + + /* cis info */ + ulong msec; /* time of last slotinfo call */ + char verstr[512]; /* version string */ + int ncfg; /* number of configurations */ + struct { + ushort cpresent; /* config registers present */ + ulong caddr; /* relative address of config registers */ + } cfg[8]; + int nctab; /* number of config table entries */ + PCMconftab ctab[8]; + PCMconftab *def; /* default conftab */ + + /* memory maps */ + Lock mlock; /* lock down the maps */ + int time; + PCMmap mmap[4]; /* maps, last is always for the kernel */ +}; diff --git a/os/boot/pc/l.s b/os/boot/pc/l.s index 0269e92e..b0f06d69 100644 --- a/os/boot/pc/l.s +++ b/os/boot/pc/l.s @@ -837,6 +837,10 @@ TEXT hello(SB), $0 BYTE $'B'; BYTE $'e'; BYTE $'l'; BYTE $'l'; BYTE $' '; BYTE $'L'; BYTE $'a'; BYTE $'b'; BYTE $'s'; +#ifdef PXE + BYTE $' '; BYTE $'b'; BYTE $'y'; BYTE $' '; + BYTE $'P'; BYTE $'X'; BYTE $'E'; +#endif BYTE $'\r'; BYTE $'\n'; BYTE $'\z'; @@ -1002,6 +1006,7 @@ TEXT now16real(SB), $0 TEXT realmodeintrinst(SB), $0 INT $0x00 + /* save the registers after the call */ LWI(0x7bfc, rSP) diff --git a/os/boot/pc/lib.h b/os/boot/pc/lib.h index a011b5e4..eea74e3e 100644 --- a/os/boot/pc/lib.h +++ b/os/boot/pc/lib.h @@ -1,3 +1,5 @@ +#define offsetof(s, m) (ulong)(&(((s*)0)->m)) + /* * functions (possibly) linked in, complete, from libc. */ @@ -5,17 +7,17 @@ /* * mem routines */ -extern void* memccpy(void*, void*, int, long); -extern void* memset(void*, int, long); -extern int memcmp(void*, void*, long); -extern void* memmove(void*, void*, long); -extern void* memchr(void*, int, long); +extern void* memccpy(void*, void*, int, ulong); +extern void* memset(void*, int, ulong); +extern int memcmp(void*, void*, ulong); +extern void* memmove(void*, void*, ulong); +extern void* memchr(void*, int, ulong); /* * string routines */ extern char* strcat(char*, char*); -extern char* strchr(char*, char); +extern char* strchr(char*, int); extern int strcmp(char*, char*); extern char* strcpy(char*, char*); extern char* strncat(char*, char*, long); @@ -51,6 +53,7 @@ extern int sprint(char*, char*, ...); extern int snprint(char*, int, char*, ...); extern int fmtinstall(int, int (*)(Fmt*)); +#pragma varargck argpos addconf 1 #pragma varargck argpos fmtprint 2 #pragma varargck argpos print 1 #pragma varargck argpos seprint 3 @@ -94,9 +97,10 @@ extern int fmtinstall(int, int (*)(Fmt*)); * one-of-a-kind */ extern int atoi(char*); -extern ulong getcallerpc(void*); +extern uintptr getcallerpc(void*); extern long strtol(char*, char**, int); extern ulong strtoul(char*, char**, int); +extern uvlong strtoull(char*, char**, int); extern long end; #define NAMELEN 28 diff --git a/os/boot/pc/load.c b/os/boot/pc/load.c index 575c1205..5d071f59 100644 --- a/os/boot/pc/load.c +++ b/os/boot/pc/load.c @@ -4,10 +4,23 @@ #include "dat.h" #include "fns.h" #include "io.h" - +#include "sd.h" #include "fs.h" -static char *diskparts[] = { "dos", "9fat", "fs", "data", "cdboot", 0 }; +#ifndef VERBOSE +#define VERBOSE 0 +#endif + +/* + * "cache" must be in this list so that 9load will pass the definition of + * the cache partition into the kernel so that the disk named by the `cfs' + * variable in plan9.ini can be seen in all circumstances before termrc + * sets up all the disk partitions. In particular, if it's on an odd-ball + * disk like sd10 rather than sdC0, this is needed. + */ +static char *diskparts[] = { + "dos", "9fat", "fs", "data", "cdboot", "cache", 0 +}; static char *etherparts[] = { "*", 0 }; static char *diskinis[] = { @@ -20,6 +33,7 @@ static char *etherinis[] = { 0 }; +/* ordering: devbios must be called before devsd calls sdbios */ Type types[] = { { Tfloppy, Fini|Ffs, @@ -29,14 +43,6 @@ Type types[] = { diskparts, diskinis, }, - { Tcd, - Fini|Ffs, - cdinit, sdinitdev, - sdgetfspart, sdaddconf, sdboot, - sdprintdevs, - diskparts, - diskinis, - }, { Tether, Fini|Fbootp, etherinit, etherinitdev, @@ -45,6 +51,22 @@ Type types[] = { etherparts, etherinis, }, + { Tbios, + Fini|Ffs, + biosinit, biosinitdev, + biosgetfspart, nil, biosboot, + biosprintdevs, + diskparts, + diskinis, + }, + { Tcd, + Fini|Ffs, + cdinit, sdinitdev, + sdgetfspart, sdaddconf, sdboot, + sdprintdevs, + diskparts, + diskinis, + }, { Tsd, Fini|Ffs, sdinit, sdinitdev, @@ -63,14 +85,35 @@ Type types[] = { }, }; -#include "sd.h" +static char *typenm[] = { + [Tnil] "nil", + [Tfloppy] "floppy", + [Tsd] "sd", + [Tether] "ether", + [Tcd] "cd", + [Tbios] "bios", +}; + +static char * +typename(int type) +{ + if (type < 0 || type >= nelem(typenm) || typenm[type] == nil) + return "**gok**"; + return typenm[type]; +} extern SDifc sdataifc; +extern SDifc sdiahciifc; +extern SDifc sdaoeifc; +extern SDifc sdbiosifc; #ifdef NOSCSI SDifc* sdifc[] = { &sdataifc, + &sdiahciifc, + &sdbiosifc, + &sdaoeifc, nil, }; @@ -78,10 +121,14 @@ SDifc* sdifc[] = { extern SDifc sdmylexifc; extern SDifc sd53c8xxifc; + SDifc* sdifc[] = { &sdataifc, + &sdiahciifc, &sdmylexifc, &sd53c8xxifc, + &sdbiosifc, + &sdaoeifc, nil, }; @@ -137,6 +184,8 @@ int scsi0port; char *defaultpartition; int iniread; +int debugload; + static Medium* parse(char *line, char **file) { @@ -179,6 +228,7 @@ boot(Medium *mp, char *file) } sprint(BOOTLINE, "%s!%s", mp->name, file); + print("booting %s!%s\n", mp->name, file); return (*mp->type->boot)(mp->dev, file, &b); } @@ -216,7 +266,8 @@ probe(int type, int flag, int dev) return mp; } } - + if (debugload) + print("probing %s...", typename(tp->type)); if((tp->flag & Fprobe) == 0){ tp->flag |= Fprobe; tp->mask = (*tp->init)(); @@ -276,25 +327,33 @@ main(void) alarminit(); meminit(0); spllo(); + consinit("0", "9600"); kbdinit(); - if((ulong)&end > (KZERO|(640*1024))) panic("i'm too big\n"); readlsconf(); + print("initial probe, to find plan9.ini..."); + /* find and read plan9.ini, setting configuration variables */ for(tp = types; tp->type != Tnil; tp++){ - //if(tp->type == Tether) - // continue; + /* skip bios until we have read plan9.ini */ + if(!pxe && tp->type == Tether || tp->type == Tbios) + continue; + if (VERBOSE) + print("probing %s...", typename(tp->type)); if((mp = probe(tp->type, Fini, Dany)) && (mp->flag & Fini)){ print("using %s!%s!%s\n", mp->name, mp->part, mp->ini); iniread = !dotini(mp->inifs); break; } } + print("\n"); apminit(); + debugload = getconf("*debugload") != nil; if((p = getconf("console")) != nil) consinit(p, getconf("baud")); + devpccardlink(); devi82365link(); @@ -304,9 +363,11 @@ main(void) * have boot devices for parse. */ probe(Tany, Fnone, Dany); + if (debugload) + print("end disk probe\n"); tried = 0; mode = Mauto; - + p = getconf("bootfile"); if(p != 0) { @@ -330,10 +391,14 @@ done: flag &= ~Fbootp; if((mp = probe(Tany, flag, Dany)) && mp->type->type != Tfloppy) boot(mp, ""); + if (debugload) + print("end auto probe\n"); } def[0] = 0; probe(Tany, Fnone, Dany); + if (debugload) + print("end final probe\n"); if(p = getconf("bootdef")) strcpy(def, p); @@ -386,7 +451,7 @@ cistrcmp(char *a, char *b) for(;;){ ac = *a++; bc = *b++; - + if(ac >= 'A' && ac <= 'Z') ac = 'a' + (ac - 'A'); if(bc >= 'A' && bc <= 'Z') @@ -425,7 +490,7 @@ cistrncmp(char *a, char *b, int n) return 0; } -#define PSTART (12*1024*1024) +#define PSTART ( 8*1024*1024) #define PEND (16*1024*1024) ulong palloc = PSTART; @@ -447,7 +512,7 @@ ialloc(ulong n, int align) palloc = p+n; if(palloc > PEND) - panic("ialloc(%lud, %d) called from 0x%lux\n", + panic("ialloc(%lud, %d) called from %#p\n", n, align, getcallerpc(&n)); return memset((void*)(p|KZERO), 0, n); } @@ -458,7 +523,7 @@ xspanalloc(ulong size, int align, ulong span) ulong a, v; if((palloc + (size+align+span)) > PEND) - panic("xspanalloc(%lud, %d, 0x%lux) called from 0x%lux\n", + panic("xspanalloc(%lud, %d, 0x%lux) called from %#p\n", size, align, span, getcallerpc(&size)); a = (ulong)ialloc(size+align+span, 0); @@ -492,7 +557,7 @@ allocb(int size) } if(bp == 0){ if((palloc + (sizeof(Block)+size+64)) > PEND) - panic("allocb(%d) called from 0x%lux\n", + panic("allocb(%d) called from %#p\n", size, getcallerpc(&size)); bp = ialloc(sizeof(Block)+size+64, 0); addr = (ulong)bp; @@ -546,9 +611,8 @@ warp9(ulong entry) floppydetach(); if(sddetach) sddetach(); - consdrain(); - + splhi(); trapdisable(); diff --git a/os/boot/pc/mem.h b/os/boot/pc/mem.h index d33fee0e..15760c0c 100644 --- a/os/boot/pc/mem.h +++ b/os/boot/pc/mem.h @@ -34,8 +34,8 @@ #define CPU0PTE 0x80003000 /* bootstrap processor PTE's for 0-4MB */ #define MACHADDR 0x80004000 /* as seen by current processor */ #define CPU0MACH 0x80005000 /* Mach for bootstrap processor */ -#define MACHSIZE (BY2PG*8) /* stack size */ - +#define BIOSXCHG 0x80006000 /* To exchange data with the BIOS */ +#define MACHSIZE (BY2PG*8) /* stack size */ /* * Address spaces diff --git a/os/boot/pc/mkfile b/os/boot/pc/mkfile index 57eef41e..b0fdb53e 100644 --- a/os/boot/pc/mkfile +++ b/os/boot/pc/mkfile @@ -46,9 +46,11 @@ LOAD=\ 8250.$O\ apm.$O\ boot.$O\ - devpccard.$O\ + cis.$O\ conf.$O\ + devbios.$O\ devi82365.$O\ + devpccard.$O\ devsd.$O\ inflate.$O\ load.$O\ @@ -58,7 +60,10 @@ LOAD=\ sdata.$O\ sdmylex.$O\ sd53c8xx.$O\ + sdiahci.$O\ sdscsi.$O\ + sdaoe.$O\ + sdbios.$O\ ETHER=\ bootp.$O\ @@ -71,14 +76,17 @@ ETHER=\ ether8003.$O\ ether8139.$O\ ether8169.$O\ + ether82563.$O\ ether82557.$O\ ether83815.$O\ ether8390.$O\ etherec2t.$O\ etherelnk3.$O\ + etherga620.$O\ etherigbe.$O\ ethermii.$O\ etherrhine.$O\ + etherdp83820.$O\ BCOM=\ bcom.$O\ @@ -96,8 +104,9 @@ HFILES=\ dat.h\ fns.h\ io.h\ + aoe.h\ -CFLAGS=-FVw -I. -I$ROOT/Inferno/$OBJTYPE/include -I$ROOT/include +CFLAGS=-FVTw -I. -I$ROOT/Inferno/$OBJTYPE/include -I$ROOT/include all:V: $TARG diff --git a/os/boot/pc/noether.c b/os/boot/pc/noether.c index 2162d1d4..b607b5bc 100644 --- a/os/boot/pc/noether.c +++ b/os/boot/pc/noether.c @@ -28,6 +28,12 @@ etherrxpkt(int, Etherpkt*, int) } int +ethertxpkt(int, Etherpkt*, int, int) +{ + return -1; +} + +int bootpboot(int, char*, Boot*) { return -1; diff --git a/os/boot/pc/part.c b/os/boot/pc/part.c index 8c703ae8..9200e3d4 100644 --- a/os/boot/pc/part.c +++ b/os/boot/pc/part.c @@ -89,8 +89,8 @@ oldp9part(SDunit *unit) for(i = 1; i < n && unit->npart < SDnpart; i++){ if(getfields(line[i], field, 3, ' ') != 3) break; - start = strtoul(field[1], 0, 0); - end = strtoul(field[2], 0, 0); + start = strtoull(field[1], 0, 0); + end = strtoull(field[2], 0, 0); if(start >= end || end > unit->sectors) break; sdaddpart(unit, field[0], start, end); @@ -103,7 +103,7 @@ p9part(SDunit *unit, char *name) { SDpart *p; char *field[4], *line[Npart+1]; - ulong start, end; + uvlong start, end; int i, n; p = sdfindpart(unit, name); @@ -125,8 +125,8 @@ p9part(SDunit *unit, char *name) break; if(getfields(line[i], field, 4, ' ') != 4) break; - start = strtoul(field[2], 0, 0); - end = strtoul(field[3], 0, 0); + start = strtoull(field[2], 0, 0); + end = strtoull(field[3], 0, 0); if(start >= end || end > unit->sectors) break; sdaddpart(unit, field[1], p->start+start, p->start+end); diff --git a/os/boot/pc/pbs.s b/os/boot/pc/pbs.s index fde5ec39..bd95a04d 100644 --- a/os/boot/pc/pbs.s +++ b/os/boot/pc/pbs.s @@ -367,6 +367,6 @@ TEXT bootfile(SB), $0 /* "PBS..." */ TEXT confidence(SB), $0 - BYTE $'P'; BYTE $'B'; BYTE $'S'; BYTE $'.'; - BYTE $'.'; BYTE $'.'; + BYTE $'P'; BYTE $'B'; BYTE $'S'; BYTE $'1'; + BYTE $'.'; BYTE $'.'; BYTE $'.'; BYTE $'\z'; diff --git a/os/boot/pc/pbsdisklba.s b/os/boot/pc/pbsdisklba.s index 357abd00..c3712f82 100644 --- a/os/boot/pc/pbsdisklba.s +++ b/os/boot/pc/pbsdisklba.s @@ -111,7 +111,7 @@ _start0x3E: /* rCX contains 0x0001 */ SBPWI(0x0010, Xdap+0) /* reserved + packet size */ - SBPWI(rCX, Xdap+2) /* reserved + # of blocks to transfer */ + SBPW(rCX, Xdap+2) /* reserved + # of blocks to transfer */ DEC(rCX) SBPW(rCX, Xdap+12) diff --git a/os/boot/pc/pbslba.s b/os/boot/pc/pbslba.s index 56388868..4f7b8325 100644 --- a/os/boot/pc/pbslba.s +++ b/os/boot/pc/pbslba.s @@ -24,6 +24,7 @@ * FAT directory entry. */ #define Dname 0x00 +#define Dnamesz 0x0B #define Dext 0x08 #define Dattr 0x0B #define Dtime 0x16 @@ -125,7 +126,7 @@ TEXT _nxt(SB), $0 /* rCX contains 0x0001 */ SBPWI(0x0010, Xdap+0) /* reserved + packet size */ - SBPWI(rCX, Xdap+2) /* reserved + # of blocks to transfer */ + SBPW(rCX, Xdap+2) /* reserved + # of blocks to transfer */ DEC(rCX) SBPW(rCX, Xdap+12) @@ -147,7 +148,7 @@ _jmp00: _cmp00: PUSHR(rDI) /* save for later if it matches */ LWI(bootfile(SB), rSI) - LWI(Dattr, rCX) + LWI(Dnamesz, rCX) REP CMPSB POPR(rDI) @@ -357,6 +358,6 @@ TEXT bootfile(SB), $0 /* "PBS..." */ TEXT confidence(SB), $0 - BYTE $'P'; BYTE $'B'; BYTE $'S'; BYTE $'.'; - BYTE $'.'; BYTE $'.'; + BYTE $'P'; BYTE $'B'; BYTE $'S'; BYTE $'2'; + BYTE $'.'; BYTE $'.'; BYTE $'.'; BYTE $'\z'; diff --git a/os/boot/pc/pci.c b/os/boot/pc/pci.c index c7b9eda5..a83a10fa 100644 --- a/os/boot/pc/pci.c +++ b/os/boot/pc/pci.c @@ -23,6 +23,16 @@ enum { /* configuration mechanism #1 */ MaxUBN = 255, }; +enum +{ /* command register */ + IOen = (1<<0), + MEMen = (1<<1), + MASen = (1<<2), + MemWrInv = (1<<4), + PErrEn = (1<<6), + SErrEn = (1<<8), +}; + static Lock pcicfglock; static Lock pcicfginitlock; static int pcicfgmode = -1; @@ -145,7 +155,8 @@ pciscan(int bno, Pcidev** list) *list = head; for(p = head; p != nil; p = p->link){ /* - * Find PCI-PCI and PCI-Cardbus bridges and recursively descend the tree. + * Find PCI-PCI and PCI-Cardbus bridges + * and recursively descend the tree. */ if(p->ccrb != 0x06 || p->ccru != 0x04) continue; @@ -181,7 +192,16 @@ pciscan(int bno, Pcidev** list) pcicfgw32(p, PciPBN, l); } else{ - maxubn = ubn; + /* + * You can't go back. + * This shouldn't be possible, but the + * Iwill DK8-HTX seems to have subordinate + * bus numbers which get smaller on the + * way down. Need to look more closely at + * this. + */ + if(ubn > maxubn) + maxubn = ubn; pciscan(sbn, &p->bridge); } } @@ -189,7 +209,18 @@ pciscan(int bno, Pcidev** list) return maxubn; } -static uchar +static uchar +null_link(Pcidev *, uchar ) +{ + return 0; +} + +static void +null_init(Pcidev *, uchar , uchar ) +{ +} + +static uchar pIIx_link(Pcidev *router, uchar link) { uchar pirq; @@ -199,13 +230,13 @@ pIIx_link(Pcidev *router, uchar link) return (pirq < 16)? pirq: 0; } -static void +static void pIIx_init(Pcidev *router, uchar link, uchar irq) { pcicfgw8(router, link, irq); } -static uchar +static uchar via_link(Pcidev *router, uchar link) { uchar pirq; @@ -216,7 +247,7 @@ via_link(Pcidev *router, uchar link) return (link & 1)? (pirq >> 4): (pirq & 15); } -static void +static void via_init(Pcidev *router, uchar link, uchar irq) { uchar pirq; @@ -227,7 +258,7 @@ via_init(Pcidev *router, uchar link, uchar irq) pcicfgw8(router, 0x55 + (link>>1), pirq); } -static uchar +static uchar opti_link(Pcidev *router, uchar link) { uchar pirq = 0; @@ -238,7 +269,7 @@ opti_link(Pcidev *router, uchar link) return (link & 0x10)? (pirq >> 4): (pirq & 15); } -static void +static void opti_init(Pcidev *router, uchar link, uchar irq) { uchar pirq; @@ -249,7 +280,7 @@ opti_init(Pcidev *router, uchar link, uchar irq) pcicfgw8(router, 0xb8 + (link >> 5), pirq); } -static uchar +static uchar ali_link(Pcidev *router, uchar link) { /* No, you're not dreaming */ @@ -261,7 +292,7 @@ ali_link(Pcidev *router, uchar link) return (link & 1)? map[pirq&15]: map[pirq>>4]; } -static void +static void ali_init(Pcidev *router, uchar link, uchar irq) { /* Inverse of map in ali_link */ @@ -274,7 +305,7 @@ ali_init(Pcidev *router, uchar link, uchar irq) pcicfgw8(router, 0x48 + ((link-1)>>1), pirq); } -static uchar +static uchar cyrix_link(Pcidev *router, uchar link) { uchar pirq; @@ -284,7 +315,7 @@ cyrix_link(Pcidev *router, uchar link) return ((link & 1)? pirq >> 4: pirq & 15); } -static void +static void cyrix_init(Pcidev *router, uchar link, uchar irq) { uchar pirq; @@ -295,64 +326,46 @@ cyrix_init(Pcidev *router, uchar link, uchar irq) pcicfgw8(router, 0x5c + (link>>1), pirq); } -enum { - Intel = 0x8086, - Intel_82371FB_0 = 0x122e, - Intel_82371MX_0 = 0x1234, - Intel_82371SB_0 = 0x7000, - Intel_82371AB_0 = 0x7110, - Intel_82443MX_1 = 0x7198, - Intel_82801AA_0 = 0x2410, - Intel_82801AB_0 = 0x2420, - Intel_82801BA_0 = 0x2440, - Intel_82801BAM_0 = 0x244c, - Intel_82801CAM_0 = 0x248c, - Intel_82801DBM_0 = 0x24cc, - Intel_82801EB_0 = 0x24d0, - Intel_82801FB_0 = 0x2640, - Viatech = 0x1106, - Via_82C586_0 = 0x0586, - Via_82C596 = 0x0596, - Via_82C686 = 0x0686, - Opti = 0x1045, - Opti_82C700 = 0xc700, - Al = 0x10b9, - Al_M1533 = 0x1533, - SI = 0x1039, - SI_503 = 0x0008, - SI_496 = 0x0496, - Cyrix = 0x1078, - Cyrix_5530_Legacy = 0x0100, -}; - typedef struct { ushort sb_vid, sb_did; uchar (*sb_translate)(Pcidev *, uchar); - void (*sb_initialize)(Pcidev *, uchar, uchar); + void (*sb_initialize)(Pcidev *, uchar, uchar); } bridge_t; static bridge_t southbridges[] = { -{ Intel, Intel_82371FB_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82371MX_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82371SB_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82371AB_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82443MX_1, pIIx_link, pIIx_init }, -{ Intel, Intel_82801AA_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82801AB_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82801BA_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82801BAM_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82801CAM_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82801DBM_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82801EB_0, pIIx_link, pIIx_init }, -{ Intel, Intel_82801FB_0, pIIx_link, pIIx_init }, -{ Viatech, Via_82C586_0, via_link, via_init }, -{ Viatech, Via_82C596, via_link, via_init }, -{ Viatech, Via_82C686, via_link, via_init }, -{ Opti, Opti_82C700, opti_link, opti_init }, -{ Al, Al_M1533, ali_link, ali_init }, -{ SI, SI_503, pIIx_link, pIIx_init }, -{ SI, SI_496, pIIx_link, pIIx_init }, -{ Cyrix, Cyrix_5530_Legacy, cyrix_link, cyrix_init } + { 0x8086, 0x122e, pIIx_link, pIIx_init }, // Intel 82371FB + { 0x8086, 0x1234, pIIx_link, pIIx_init }, // Intel 82371MX + { 0x8086, 0x7000, pIIx_link, pIIx_init }, // Intel 82371SB + { 0x8086, 0x7110, pIIx_link, pIIx_init }, // Intel 82371AB + { 0x8086, 0x7198, pIIx_link, pIIx_init }, // Intel 82443MX (fn 1) + { 0x8086, 0x2410, pIIx_link, pIIx_init }, // Intel 82801AA + { 0x8086, 0x2420, pIIx_link, pIIx_init }, // Intel 82801AB + { 0x8086, 0x2440, pIIx_link, pIIx_init }, // Intel 82801BA + { 0x8086, 0x244c, pIIx_link, pIIx_init }, // Intel 82801BAM + { 0x8086, 0x2480, pIIx_link, pIIx_init }, // Intel 82801CA + { 0x8086, 0x248c, pIIx_link, pIIx_init }, // Intel 82801CAM + { 0x8086, 0x24c0, pIIx_link, pIIx_init }, // Intel 82801DBL + { 0x8086, 0x24cc, pIIx_link, pIIx_init }, // Intel 82801DBM + { 0x8086, 0x24d0, pIIx_link, pIIx_init }, // Intel 82801EB + { 0x8086, 0x2640, pIIx_link, pIIx_init }, // Intel 82801FB + { 0x8086, 0x27b8, pIIx_link, pIIx_init }, // Intel 82801GB + { 0x8086, 0x27b9, pIIx_link, pIIx_init }, // Intel 82801GBM + { 0x1106, 0x0586, via_link, via_init }, // Viatech 82C586 + { 0x1106, 0x0596, via_link, via_init }, // Viatech 82C596 + { 0x1106, 0x0686, via_link, via_init }, // Viatech 82C686 + { 0x1106, 0x3227, via_link, via_init }, // Viatech VT8237 + { 0x1045, 0xc700, opti_link, opti_init }, // Opti 82C700 + { 0x10b9, 0x1533, ali_link, ali_init }, // Al M1533 + { 0x1039, 0x0008, pIIx_link, pIIx_init }, // SI 503 + { 0x1039, 0x0496, pIIx_link, pIIx_init }, // SI 496 + { 0x1078, 0x0100, cyrix_link, cyrix_init }, // Cyrix 5530 Legacy + + { 0x1002, 0x4377, nil, nil }, // ATI Radeon Xpress 200M + { 0x1002, 0x4372, nil, nil }, // ATI SB400 + { 0x1022, 0x746B, nil, nil }, // AMD 8111 + { 0x10DE, 0x00D1, nil, nil }, // NVIDIA nForce 3 + { 0x10DE, 0x00E0, nil, nil }, // NVIDIA nForce 3 250 Series + { 0x1166, 0x0200, nil, nil }, // ServerWorks ServerSet III LE }; typedef struct { @@ -423,7 +436,7 @@ pcirouting(void) vid, did); return; } - + pciirqs = (r->rt_pciirqs[1] << 8)|r->rt_pciirqs[0]; size = (r->rt_size[1] << 8)|r->rt_size[0]; @@ -443,12 +456,12 @@ pcirouting(void) // obtaining the Pcidev structure. tbdf = (BusPCI << 24)|(e->e_bus << 16)|((e->e_dev | fn) << 8); vdid = pcicfgrw32(tbdf, PciVID, 0, 1); - if (vdid == 0xFFFFFFFF || vdid == 0) + if (vdid == 0xFFFFFFFF || vdid == 0) continue; vid = vdid; did = vdid >> 16; - + pci = nil; while ((pci = pcimatch(pci, vid, did)) != nil) { @@ -456,13 +469,13 @@ pcirouting(void) continue; pin = pcicfgr8(pci, PciINTP); - if (pin == 0 || pin == 0xff) + if (pin == 0 || pin == 0xff) continue; - + m = &e->e_maps[(pin - 1) * 3]; irq = southbridge->sb_translate(sbpci, m[0]); if (irq) { - print("pcirouting: %.4uX/%.4uX at pin %d irq %d\n", + print("pcirouting: %.4uX/%.4uX at pin %d irq %d\n", vid, did, pin, irq); pcicfgw8(pci, PciINTL, irq); pci->intl = irq; @@ -521,7 +534,7 @@ pcicfginit(void) } outb(PciCSE, n); } - + if(pcicfgmode < 0) goto out; @@ -841,12 +854,149 @@ pcireset(void) } void +pcisetioe(Pcidev* p) +{ + p->pcr |= IOen; + pcicfgw16(p, PciPCR, p->pcr); +} + +void +pciclrioe(Pcidev* p) +{ + p->pcr &= ~IOen; + pcicfgw16(p, PciPCR, p->pcr); +} + +void pcisetbme(Pcidev* p) { - int pcr; + p->pcr |= MASen; + pcicfgw16(p, PciPCR, p->pcr); +} + +void +pciclrbme(Pcidev* p) +{ + p->pcr &= ~MASen; + pcicfgw16(p, PciPCR, p->pcr); +} + +void +pcisetmwi(Pcidev* p) +{ + p->pcr |= MemWrInv; + pcicfgw16(p, PciPCR, p->pcr); +} + +void +pciclrmwi(Pcidev* p) +{ + p->pcr &= ~MemWrInv; + pcicfgw16(p, PciPCR, p->pcr); +} + +static int +pcigetpmrb(Pcidev* p) +{ + int ptr; + + if(p->pmrb != 0) + return p->pmrb; + p->pmrb = -1; + + /* + * If there are no extended capabilities implemented, + * (bit 4 in the status register) assume there's no standard + * power management method. + * Find the capabilities pointer based on PCI header type. + */ + if(!(pcicfgr16(p, PciPSR) & 0x0010)) + return -1; + switch(pcicfgr8(p, PciHDT)){ + default: + return -1; + case 0: /* all other */ + case 1: /* PCI to PCI bridge */ + ptr = 0x34; + break; + case 2: /* CardBus bridge */ + ptr = 0x14; + break; + } + ptr = pcicfgr32(p, ptr); + + while(ptr != 0){ + /* + * Check for validity. + * Can't be in standard header and must be double + * word aligned. + */ + if(ptr < 0x40 || (ptr & ~0xFC)) + return -1; + if(pcicfgr8(p, ptr) == 0x01){ + p->pmrb = ptr; + return ptr; + } + + ptr = pcicfgr8(p, ptr+1); + } + + return -1; +} - pcr = pcicfgr16(p, PciPCR); - pcr |= 0x0004; - pcicfgw16(p, PciPCR, pcr); +int +pcigetpms(Pcidev* p) +{ + int pmcsr, ptr; + + if((ptr = pcigetpmrb(p)) == -1) + return -1; + + /* + * Power Management Register Block: + * offset 0: Capability ID + * 1: next item pointer + * 2: capabilities + * 4: control/status + * 6: bridge support extensions + * 7: data + */ + pmcsr = pcicfgr16(p, ptr+4); + + return pmcsr & 0x0003; } +int +pcisetpms(Pcidev* p, int state) +{ + int ostate, pmc, pmcsr, ptr; + + if((ptr = pcigetpmrb(p)) == -1) + return -1; + + pmc = pcicfgr16(p, ptr+2); + pmcsr = pcicfgr16(p, ptr+4); + ostate = pmcsr & 0x0003; + pmcsr &= ~0x0003; + + switch(state){ + default: + return -1; + case 0: + break; + case 1: + if(!(pmc & 0x0200)) + return -1; + break; + case 2: + if(!(pmc & 0x0400)) + return -1; + break; + case 3: + break; + } + pmcsr |= state; + pcicfgw16(p, ptr+4, pmcsr); + + return ostate; +} diff --git a/os/boot/pc/sd.h b/os/boot/pc/sd.h index a19ac689..25a19cf4 100644 --- a/os/boot/pc/sd.h +++ b/os/boot/pc/sd.h @@ -8,8 +8,8 @@ typedef struct SDreq SDreq; typedef struct SDunit SDunit; typedef struct SDpart { - ulong start; - ulong end; + uvlong start; + uvlong end; char name[NAMELEN]; char user[NAMELEN]; ulong perm; @@ -25,7 +25,7 @@ typedef struct SDunit { // Rendez rendez; // QLock ctl; - ulong sectors; + uvlong sectors; ulong secsize; SDpart* part; int npart; /* of valid partitions */ @@ -121,7 +121,6 @@ void tsleep(void*, int(*)(void*), void*, int); #define wakeup(x) while(0) extern long sdbio(SDunit *unit, SDpart *pp, void *a, long len, vlong off); void partition(SDunit*); -void addpartconf(SDunit*); SDpart* sdfindpart(SDunit*, char*); -void sdaddpart(SDunit*, char*, ulong, ulong); +void sdaddpart(SDunit*, char*, uvlong, uvlong); void* sdmalloc(void*, ulong); diff --git a/os/boot/pc/sd53c8xx.c b/os/boot/pc/sd53c8xx.c index b9dc3e9a..cc47edf0 100644 --- a/os/boot/pc/sd53c8xx.c +++ b/os/boot/pc/sd53c8xx.c @@ -1864,28 +1864,32 @@ static Variant variant[] = { { SYM_1011_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 }, }; -#define offsetof(s, t) ((ulong)&((s *)0)->t) static int xfunc(Controller *c, enum na_external x, unsigned long *v) { - switch (x) - { + switch (x) { + default: + print("xfunc: can't find external %d\n", x); + return 0; case X_scsi_id_buf: - *v = offsetof(Dsa, scsi_id_buf[0]); return 1; + *v = offsetof(Dsa, scsi_id_buf[0]); + break; case X_msg_out_buf: - *v = offsetof(Dsa, msg_out_buf); return 1; + *v = offsetof(Dsa, msg_out_buf); + break; case X_cmd_buf: - *v = offsetof(Dsa, cmd_buf); return 1; + *v = offsetof(Dsa, cmd_buf); + break; case X_data_buf: - *v = offsetof(Dsa, data_buf); return 1; + *v = offsetof(Dsa, data_buf); + break; case X_status_buf: - *v = offsetof(Dsa, status_buf); return 1; + *v = offsetof(Dsa, status_buf); + break; case X_dsa_head: - *v = DMASEG(&c->dsalist.head[0]); return 1; - default: - print("xfunc: can't find external %d\n", x); - return 0; + *v = DMASEG(&c->dsalist.head[0]); + break; } return 1; } @@ -1960,7 +1964,7 @@ sympnp(void) } if(v >= &variant[nelem(variant)]) continue; - print("sd53c8xx: %s rev. 0x%2.2x intr=%d command=%4.4luX\n", + print("sd53c8xx: %s rev. 0x%2.2x intr=%d command=%4.4uX\n", v->name, p->rid, p->intl, p->pcr); regpa = p->mem[1].bar; diff --git a/os/boot/pc/sdaoe.c b/os/boot/pc/sdaoe.c new file mode 100644 index 00000000..04375b30 --- /dev/null +++ b/os/boot/pc/sdaoe.c @@ -0,0 +1,734 @@ +/* + * aoe sd bootstrap driver, copyright © 2007 coraid + */ + +#include "u.h" +#include "mem.h" +#include "lib.h" +#include "dat.h" +#include "fns.h" +#include "io.h" +#include "sd.h" +#include "aoe.h" + +#define uprint(...) snprint(up->genbuf, sizeof up->genbuf, __VA_ARGS__); + +enum { + Nctlr = 4, +}; + +enum { + /* sync with ahci.h */ + Dllba = 1<<0, + Dsmart = 1<<1, + Dpower = 1<<2, + Dnop = 1<<3, + Datapi = 1<<4, + Datapi16= 1<<5, +}; + +enum { + Tfree = -1, + Tmgmt, +}; + +typedef struct Ctlr Ctlr; +struct Ctlr{ + Ctlr *next; + SDunit *unit; + + int ctlrno; + int major; + int minor; + uchar ea[Eaddrlen]; + ushort lasttag; + + ulong vers; + uchar mediachange; + uchar flag; + uchar smart; + uchar smartrs; + uchar feat; + + uvlong sectors; + char serial[20+1]; + char firmware[8+1]; + char model[40+1]; + char ident[0x100]; +}; + +static Ctlr *head; +static Ctlr *tail; + +static int aoeether[10]; + +SDifc sdaoeifc; + +static void +hnputs(uchar *p, ushort i) +{ + p[0] = i >> 8; + p[1] = i; +} + +static void +hnputl(uchar *p, ulong i) +{ + p[0] = i >> 24; + p[1] = i >> 16; + p[2] = i >> 8; + p[3] = i; +} + +static ushort +nhgets(uchar *p) +{ + return *p<<8 | p[1]; +} + +static ulong +nhgetl(uchar *p) +{ + return p[0]<<24 | p[1]<<16 | p[2]<<8 | p[3]; +} + +static int +newtag(Ctlr *d) +{ + int t; + + for(;;){ + t = ++d->lasttag << 16; + t |= m->ticks & 0xffff; + switch(t) { + case Tfree: + case Tmgmt: + break; + default: + return t; + } + } +} + +static int +hset(Ctlr *d, Aoehdr *h, int cmd) +{ + int tag; + + memmove(h->dst, d->ea, Eaddrlen); + hnputs(h->type, Aoetype); + h->verflag = Aoever << 4; + hnputs(h->major, d->major); + h->minor = d->minor; + h->cmd = cmd; + hnputl(h->tag, tag = newtag(d)); + return tag; +} + +static void +idmove(char *p, ushort *a, int n) +{ + int i; + char *op, *e; + + op = p; + for(i = 0; i < n / 2; i++){ + *p++ = a[i] >> 8; + *p++ = a[i]; + } + *p = 0; + while(p > op && *--p == ' ') + *p = 0; + e = p; + p = op; + while(*p == ' ') + p++; + memmove(op, p, n - (e - p)); +} + +static ushort +gbit16(void *a) +{ + uchar *i; + + i = a; + return i[1]<<8 | i[0]; +} + +static ulong +gbit32(void *a) +{ + uchar *i; + ulong j; + + i = a; + j = i[3] << 24; + j |= i[2] << 16; + j |= i[1] << 8; + j |= i[0]; + return j; +} + +static uvlong +gbit64(void *a) +{ + uchar *i; + + i = a; + return (uvlong)gbit32(i+4) << 32 | gbit32(a); +} + +static int +ataidentify(Ctlr *c, ushort *id) +{ + vlong s; + int i; + + i = gbit16(id+83) | gbit16(id+86); + if(i & (1 << 10)){ + c->feat |= Dllba; + s = gbit64(id+100); + }else + s = gbit32(id+60); + + idmove(c->serial, id+10, 20); + idmove(c->firmware, id+23, 8); + idmove(c->model, id+27, 40); + +print("aoe discovers %d.%d: %s %s\n", c->major, c->minor, c->model, c->serial); + + c->sectors = s; + c->mediachange = 1; + return 0; +} + +static void +identifydump(Aoeata *a) +{ + print("%E %E type=%.4ux verflag=%x error=%x %d.%d cmd=%d tag=%.8lux\n", + a->dst, a->src, nhgets(a->type), a->verflag, a->error, + nhgets(a->major), a->minor, a->cmd, nhgetl(a->tag)); + print(" aflag=%x errfeat=%ux scnt=%d cmdstat=%ux, lba=%d? res=%.4ux\n", + a->aflag, a->errfeat, a->scnt, a->cmdstat, 0, nhgets(a->res)); +} + +static int +idpkt(Ctlr *c, Aoeata *a) +{ + memset(a, 0, sizeof *a); + a->cmdstat = Cid; + a->scnt = 1; + a->lba[3] = 0xa0; + return hset(c, a, ACata); +} + +static int +chktag(int *out, int nout, int tag) +{ + int j; + + for(j = 0; j <= nout; j++) + if(out[j] == tag) + return 0; +print("wrong tag\n"); + for(j = 0; j <= nout; j++) + print("%.8ux != %.8ux\n", out[j], tag); + return -1; +} + +/* + * ignore the tag for identify. better than ignoring + * a response to the wrong identify request + */ +static int +identify(Ctlr *c) +{ + int tag[5], i, n; + Aoeata *a; + Etherpkt p; + + memset(&p, 0, sizeof p); + a = (Aoeata*)&p; + i = 0; + do { + if(i == 5){ + print("aoe: identify timeout\n"); + return -1; + } + tag[i] = idpkt(c, a); + ethertxpkt(c->ctlrno, &p, sizeof *a, 0); + memset(&p, 0, sizeof p); +next: + n = etherrxpkt(c->ctlrno, &p, 125); + if(n == 0){ + i++; + continue; + } + if(nhgets(a->type) != Aoetype) + goto next; + if(nhgets(a->major) != c->major || a->minor != c->minor){ + print("wrong device %d.%d want %d.%d; %d\n", + nhgets(a->major), a->minor, + c->major, c->minor, n); + goto next; + } + if(chktag(tag, i, nhgetl(a->tag)) == -1) + goto next; + if(a->cmdstat & 0xa9){ + print("aoe: ata error on identify: %2ux\n", a->cmdstat); + return -1; + } + } while (a->scnt != 1); + + c->feat = 0; + ataidentify(c, (ushort*)(a+1)); + return 0; +} + +static Ctlr* +ctlrlookup(int major, int minor) +{ + Ctlr *c; + + for(c = head; c; c = c->next) + if(c->major == major && c->minor == minor) + break; + return c; +} + +static Ctlr* +newctlr(Etherpkt *p) +{ + int major, minor; + Aoeqc *q; + Ctlr *c; + + q = (Aoeqc*)p; + if(nhgets(q->type) != Aoetype) + return 0; + major = nhgets(q->major); + minor = q->minor; + + if(major == 0xffff || minor == 0xff) + return 0; + + if(ctlrlookup(major, minor)){ + print("duplicate shelf.slot\n"); + return 0; + } + + if((c = malloc(sizeof *c)) == 0) + return 0; + c->major = major; + c->minor = minor; + memmove(c->ea, q->src, Eaddrlen); + + if(head != 0) + tail->next = c; + else + head = c; + tail = c; + return c; +} + +static void +discover(int major, int minor) +{ + int i; + Aoehdr *h; + Etherpkt p; + + for(i = 0; i < nelem(aoeether); i++){ + if(aoeether[i] == 0) + continue; + memset(&p, 0, ETHERMINTU); + h = (Aoehdr*)&p; + memset(h->dst, 0xff, sizeof h->dst); + hnputs(h->type, Aoetype); + h->verflag = Aoever << 4; + hnputs(h->major, major); + h->minor = minor; + h->cmd = ACconfig; + ethertxpkt(i, &p, ETHERMINTU, 0); + } +} + +static int +rxany(Etherpkt *p, int t) +{ + int i, n; + + for(i = 0; i < nelem(aoeether); i++){ + if(aoeether[i] == 0) + continue; + while ((n = etherrxpkt(i, p, t)) != 0) + if(nhgets(p->type) == Aoetype) + return n; + } + return 0; +} + +static int +aoeprobe(int major, int minor, SDev *s) +{ + Ctlr *ctlr; + Etherpkt p; + int n, i; + + for(i = 0;; i += 200){ + if(i > 8000) + return -1; + discover(major, minor); +again: + n = rxany(&p, 100); + if(n > 0 && (ctlr = newctlr(&p))) + break; + if(n > 0) + goto again; + } + + s->ctlr = ctlr; + s->ifc = &sdaoeifc; + s->nunit = 1; + return 0; +} + +static char *probef[32]; +static int nprobe; + +int +pnpprobeid(char *s) +{ + int id; + + if(strlen(s) < 2) + return 0; + id = 'e'; + if(s[1] == '!') + id = s[0]; + return id; +} + +int +tokenize(char *s, char **args, int maxargs) +{ + int nargs; + + for(nargs = 0; nargs < maxargs; nargs++){ + while(*s != '\0' && strchr("\t\n ", *s) != nil) + s++; + if(*s == '\0') + break; + args[nargs] = s; + while(*s != '\0' && strchr("\t\n ", *s) == nil) + s++; + if(*s != '\0') + *s++ = 0; + } + return nargs; +} + +int +aoepnp0(void) +{ + int i; + char *p, c; + + if((p = getconf("aoeif")) == nil) + return 0; +print("aoeif = %s\n", p); + nprobe = tokenize(p, probef, nelem(probef)); + for(i = 0; i < nprobe; i++){ + if(strncmp(probef[i], "ether", 5) != 0) + continue; + c = probef[i][5]; + if(c > '9' || c < '0') + continue; + aoeether[c - '0'] = 1; + } + + if((p = getconf("aoedev")) == nil) + return 0; + return nprobe = tokenize(p, probef, nelem(probef)); +} + +int +probeshelf(char *s, int *shelf, int *slot) +{ + int a, b; + char *r; + + for(r = s + strlen(s) - 1; r > s; r--) + if((*r < '0' || *r > '9') && *r != '.'){ + r++; + break; + } + a = strtoul(r, &r, 10); + if(*r++ != '.') + return -1; + b = strtoul(r, 0, 10); + + *shelf = a; + *slot = b; +print(" shelf=%d.%d\n", a, b); + return 0; +} + +Ctlr* +pnpprobe(SDev *sd) +{ + int shelf, slot; + char *p; + static int i; + + if(i >= nprobe) + return 0; + p = probef[i++]; + if(strlen(p) < 2) + return 0; + if(p[1] == '!'){ + sd->idno = p[0]; + p += 2; + } + if(probeshelf(p, &shelf, &slot) == -1 || + aoeprobe(shelf, slot, sd) == -1 || + identify(sd->ctlr) == -1) + return 0; + return sd->ctlr; +} + +/* + * we may need to pretend we found something + */ + +SDev* +aoepnp(void) +{ + int n, i, id; + char *p; + SDev *h, *t, *s; + + p = getconf("aoeif"); + if (p) + print("aoepnp: aoeif=%s\n", p); + + if((n = aoepnp0()) == 0) + n = 2; + t = h = 0; + for(i = 0; i < n; i++){ + id = 'e'; + s = malloc(sizeof *s); + if(s == 0) + break; + s->ctlr = 0; + s->idno = id; + s->ifc = &sdaoeifc; + s->nunit = 1; + pnpprobe(s); + + if(h) + t->next = s; + else + h = s; + t = s; + } + return h; +} + +static int +aoeverify(SDunit *u) +{ + Ctlr *c; + SDev *s; + + s = u->dev; + c = s->ctlr; + if(c == 0){ + aoepnp0(); + if((s->ctlr = c = pnpprobe(s)) == nil) + return 0; + } + c->mediachange = 1; + return 1; +} + +static int +aoeonline(SDunit *u) +{ + int r; + Ctlr *c; + + c = u->dev->ctlr; + if(c->mediachange){ + r = 2; + c->mediachange = 0; + u->sectors = c->sectors; + u->secsize = 512; + } else + r = 1; + return r; +} + +static int +rio(Ctlr *c, Aoeata *a, int n, int scnt) +{ + int i, tag, cmd; + + for(i = 0; i < 5; i++){ + tag = hset(c, a, ACata); + cmd = a->cmdstat; + ethertxpkt(c->ctlrno, (Etherpkt*)a, n, 0); + memset(a, 0, sizeof *a); +again: + n = etherrxpkt(c->ctlrno, (Etherpkt*)a, 125); + if(n == 0) + continue; + if(nhgets(a->type) != Aoetype || nhgetl(a->tag) != tag || + nhgets(a->major) != c->major || a->minor != c->minor) + goto again; + if(a->cmdstat & 0xa9){ + print("aoe: ata rio error: %2ux\n", a->cmdstat); + return 0; + } + switch(cmd){ + case Crd: + case Crdext: + if(n - sizeof *a < scnt * 512){ + print("aoe: runt expect %d got %d\n", + scnt*512 + sizeof *a, n); + return 0; + } + return n - sizeof *a; + case Cwr: + case Cwrext: + return scnt * 512; + default: +print("unknown cmd %ux\n", cmd); + break; + } + } + print("aoe: rio timeout\n"); + return 0; +} + +static void +putlba(Aoeata *a, vlong lba) +{ + uchar *c; + + c = a->lba; + c[0] = lba; + c[1] = lba >> 8; + c[2] = lba >> 16; + c[3] = lba >> 24; + c[4] = lba >> 32; + c[5] = lba >> 40; +} + +/* + * you'll need to loop if you want to read more than 2 sectors. for now + * i'm cheeting and not bothering with a loop. + */ +static uchar pktbuf[1024 + sizeof(Aoeata)]; + +static int +aoebuild(Ctlr *c, uchar *cmd, char *data, vlong lba, int scnt) +{ + int n; + Aoeata *a; + + memset(pktbuf, 0, sizeof pktbuf); + a = (Aoeata*)pktbuf; + hset(c, a, ACata); + putlba(a, lba); + + a->cmdstat = 0x20; + if(c->flag & Dllba){ + a->aflag |= AAFext; + a->cmdstat |= 4; + }else{ + a->lba[3] &= 0xf; + a->lba[3] |= 0xe0; /* LBA bit+obsolete 0xa0 */ + } + + n = scnt; + if(n > 2) + n = 2; + a->scnt = n; + + switch(*cmd){ + case 0x2a: + a->aflag |= AAFwrite; + a->cmdstat |= 10; + memmove(a+1, data, n*512); + n = sizeof *a + n*512; + break; + case 0x28: + n = sizeof *a; + break; + default: + print("aoe: bad cmd 0x%.2ux\n", cmd[0]); + return -1; + } + return n; +} + +static int +aoerio(SDreq *r) +{ + int size, nsec, n; + vlong lba; + char *data; + uchar *cmd; + Aoeata *a; + Ctlr *c; + SDunit *unit; + + unit = r->unit; + c = unit->dev->ctlr; + if(r->data == nil) + return SDok; + cmd = r->cmd; + + lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5]; /* sic. */ + nsec = cmd[7]<<8 | cmd[8]; + a = (Aoeata*)pktbuf; + data = r->data; + r->rlen = 0; + + for(; nsec > 0; nsec -= n){ +// print("aoebuild(%2x, %p, %lld, %d)\n", *cmd, data, lba, nsec); + size = aoebuild(c, cmd, data, lba, nsec); + if(size < 0){ + r->status = SDcheck; + return SDcheck; + } + n = a->scnt; + r->rlen += rio(c, a, size, n); + if(*cmd == 0x28) + memmove(r->data, a + 1, n * 512); + data += n * 512; + lba += n; + } + + r->status = SDok; + return SDok; +} + +SDifc sdaoeifc = { + "aoe", + + aoepnp, + nil, /* legacy */ + nil, /* id */ + nil, /* enable */ + nil, /* disable */ + + aoeverify, + aoeonline, + aoerio, + nil, + nil, + + scsibio, +}; diff --git a/os/boot/pc/sdata.c b/os/boot/pc/sdata.c index d035dc9c..4ec2f407 100644 --- a/os/boot/pc/sdata.c +++ b/os/boot/pc/sdata.c @@ -1465,7 +1465,8 @@ atapnp(void) case (0x4D69<<16)|0x105A: /* Promise Ultra/133 TX2 */ case (0x3373<<16)|0x105A: /* Promise 20378 RAID */ case (0x3149<<16)|0x1106: /* VIA VT8237 SATA/RAID */ - case (0x3112<<16)|0x1095: /* SiL 3112 SATA (DMA busted?) */ + case (0x4379<<16)|0x1002: /* ATI 4379 SATA*/ + case (0x3112<<16)|0x1095: /* SiL 3112 SATA (DMA busted?) */ case (0x3114<<16)|0x1095: /* SiL 3114 SATA/RAID */ pi = 0x85; break; @@ -1506,7 +1507,16 @@ atapnp(void) * This can probably be lumped in with the 768 above. */ /*FALLTHROUGH*/ + case (0x209A<<16)|0x1022: /* AMD CS5536 */ + case (0x01BC<<16)|0x10DE: /* nVidia nForce1 */ + case (0x0065<<16)|0x10DE: /* nVidia nForce2 */ + case (0x0085<<16)|0x10DE: /* nVidia nForce2 MCP */ case (0x00D5<<16)|0x10DE: /* nVidia nForce3 */ + case (0x00E5<<16)|0x10DE: /* nVidia nForce3 Pro */ + case (0x0035<<16)|0x10DE: /* nVidia nForce3 MCP */ + case (0x0053<<16)|0x10DE: /* nVidia nForce4 */ + case (0x0054<<16)|0x10DE: /* nVidia nForce4 SATA */ + case (0x0055<<16)|0x10DE: /* nVidia nForce4 SATA */ /* * Ditto, although it may have a different base * address for the registers (0x50?). @@ -1527,6 +1537,9 @@ atapnp(void) case (0x24CA<<16)|0x8086: /* 82801DBM (ICH4, Mobile) */ case (0x24CB<<16)|0x8086: /* 82801DB (ICH4, High-End) */ case (0x24DB<<16)|0x8086: /* 82801EB (ICH5) */ + case (0x266F<<16)|0x8086: /* 82801FB (ICH6) */ + case (0x27C4<<16)|0x8086: /* 82801GBM SATA (ICH7) */ + case (0x27C5<<16)|0x8086: /* 82801GBM SATA AHCI (ICH7) */ break; } diff --git a/os/boot/pc/sdbios.c b/os/boot/pc/sdbios.c new file mode 100644 index 00000000..fd4fe681 --- /dev/null +++ b/os/boot/pc/sdbios.c @@ -0,0 +1,165 @@ +/* + * boot driver for BIOS devices with partitions + * devbios must be called first + */ +#include "u.h" +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" +#include "ureg.h" +#include "error.h" + +#include "sd.h" +#include "fs.h" + +long biosread(Fs *, void *, long); +vlong biosseek(Fs *fs, vlong off); + +extern SDifc sdbiosifc; +extern int onlybios0, biosinited; + +int +biosverify(SDunit* ) +{ + if (onlybios0 || !biosinited) + return 0; + return 1; +} + +int +biosonline(SDunit* unit) +{ + if (onlybios0 || !biosinited || !unit) + return 0; + unit->sectors = 1UL << 30; /* a bunch */ + unit->secsize = 512; /* conventional */ + return 1; +} + +static int +biosrio(SDreq* r) +{ + int nb; + long got; + vlong len, off; + uchar *p; + Fs fs; /* just for fs->dev, which is zero */ + + if (onlybios0 || !biosinited) + return SDeio; + /* + * Most SCSI commands can be passed unchanged except for + * the padding on the end. The few which require munging + * are not used internally. Mode select/sense(6) could be + * converted to the 10-byte form but it's not worth the + * effort. Read/write(6) are easy. + */ + r->rlen = 0; + r->status = SDok; + switch(r->cmd[0]){ + case 0x08: /* read */ + case 0x28: /* read */ + if (r->cmd[0] == 0x08) + panic("biosrio: 0x08 read op\n"); + off = r->cmd[2]<<24 | r->cmd[3]<<16 | r->cmd[4]<<8 | r->cmd[5]; + nb = r->cmd[7]<<8 | r->cmd[8]; /* often 4 */ + USED(nb); /* is nb*512 == r->dlen? */ + memset(&fs, 0, sizeof fs); + biosseek(&fs, off*512); + got = biosread(&fs, r->data, r->dlen); + if (got < 0) + r->status = SDeio; + else + r->rlen = got; + break; + case 0x0A: /* write */ + case 0x2A: /* write */ + r->status = SDeio; /* boot programs don't write */ + break; + case 0x25: /* read capacity */ + /* + * Read capacity returns the LBA of the last sector. + */ + len = r->unit->sectors - 1; + p = r->data; + *p++ = len>>24; + *p++ = len>>16; + *p++ = len>>8; + *p++ = len; + len = r->unit->secsize; + *p++ = len>>24; + *p++ = len>>16; + *p++ = len>>8; + *p = len; + r->data = (char *)r->data + 8; + return SDok; + case 0x9E: /* long read capacity */ + /* + * Read capacity returns the LBA of the last sector. + */ + len = r->unit->sectors - 1; + p = r->data; + *p++ = len>>56; + *p++ = len>>48; + *p++ = len>>40; + *p++ = len>>32; + *p++ = len>>24; + *p++ = len>>16; + *p++ = len>>8; + *p++ = len; + len = r->unit->secsize; + *p++ = len>>24; + *p++ = len>>16; + *p++ = len>>8; + *p = len; + r->data = (char *)r->data + 8; + return SDok; + /* ignore others */ + } + return r->status; +} + +SDev* +biosid(SDev* sdev) +{ + for (; sdev; sdev = sdev->next) + if (sdev->ifc == &sdbiosifc) + sdev->idno = 'B'; + return sdev; +} + +static SDev* +biospnp(void) +{ + SDev *sdev; + + /* 9pxeload can't use bios int 13 calls; they wedge the machine */ + if (pxe || getconf("*nobiosload") != nil || onlybios0 || !biosinited) + return nil; + if((sdev = malloc(sizeof(SDev))) != nil) { + sdev->ifc = &sdbiosifc; + sdev->index = -1; + sdev->nunit = 1; + } + return sdev; +} + +SDifc sdbiosifc = { + "bios", /* name */ + + biospnp, /* pnp */ + nil, /* legacy */ + biosid, /* id */ + nil, /* enable */ + nil, /* disable */ + + biosverify, /* verify */ + biosonline, /* online */ + biosrio, /* rio */ + nil, /* rctl */ + nil, /* wctl */ + + scsibio, /* bio */ +}; diff --git a/os/boot/pc/sdiahci.c b/os/boot/pc/sdiahci.c new file mode 100644 index 00000000..2cf6a880 --- /dev/null +++ b/os/boot/pc/sdiahci.c @@ -0,0 +1,1668 @@ +/* + * intel/amd ahci (advanced host controller interface) sata controller + * bootstrap driver + * copyright © 2007, 2008 coraid, inc. + */ + +#include "u.h" +#include "lib.h" +#include "mem.h" +#include "dat.h" +#include "fns.h" +#include "io.h" +#include "error.h" +#include "sd.h" +#include "ahci.h" + +#define dprint(...) if(debug == 1) print(__VA_ARGS__); else USED(debug) +#define idprint(...) if(prid == 1) print(__VA_ARGS__); else USED(prid) +#define aprint(...) if(datapi == 1) print(__VA_ARGS__); else USED(datapi) + +enum { + NCtlr = 2, + NCtlrdrv= 8, + NDrive = NCtlr*NCtlrdrv, + + Read = 0, + Write +}; + +/* pci space configurtion */ +enum { + Pmap = 0x90, + Ppcs = 0x91, + Prev = 0xa8, +}; + +enum { + Tesb, + Tich, + Tsb600, +}; + +#define Intel(x) ((x) == Tesb || (x) == Tich) + +static char *tname[] = { + "63xxesb", + "ich", + "sb600", +}; + +enum { + Dnull, + Dmissing, + Dnew, + Dready, + Derror, + Dreset, + Doffline, + Dportreset, + Dlast +}; + +static char *diskstates[Dlast] = { + "null", + "missing", + "new", + "ready", + "error", + "reset", + "offline", + "portreset", +}; + +extern SDifc sdiahciifc; +typedef struct Ctlr Ctlr; + +enum { + DMautoneg, + DMsatai, + DMsataii, +}; + +static char *modename[] = { + "auto", + "satai", + "sataii", +}; + +typedef struct { + Lock; + + Ctlr *ctlr; + SDunit *unit; + char name[10]; + Aport *port; + Aportm portm; + Aportc portc; /* redundant ptr to port and portm. */ + + uchar mediachange; + uchar state; + uchar smartrs; + + uvlong sectors; + ulong intick; + int wait; + uchar mode; /* DMautoneg, satai or sataii. */ + uchar active; + + char serial[20+1]; + char firmware[8+1]; + char model[40+1]; + + ushort info[0x200]; + + int driveno; /* ctlr*NCtlrdrv + unit */ + int portno; /* ctlr port # != drive # when not all ports enabled. */ +} Drive; + +struct Ctlr { + Lock; + + int type; + int enabled; + SDev *sdev; + Pcidev *pci; + + uchar *mmio; + ulong *lmmio; + Ahba *hba; + + Drive rawdrive[NCtlrdrv]; + Drive* drive[NCtlrdrv]; + int ndrive; +}; + +static Ctlr iactlr[NCtlr]; +static SDev sdevs[NCtlr]; +static int niactlr; + +static int prid = 0; +static int datapi = 0; + +static char stab[] = { +[0] 'i', 'm', +[8] 't', 'c', 'p', 'e', +[16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X' +}; + +static void +serrstr(ulong r, char *s, char *e) +{ + int i; + + e -= 3; + for(i = 0; i < nelem(stab) && s < e; i++) + if((r & (1<<i)) && stab[i]){ + *s++ = stab[i]; + if(SerrBad & (1<<i)) + *s++ = '*'; + } + *s = 0; +} + +static char ntab[] = "0123456789abcdef"; + +static void +preg(uchar *reg, int n) +{ + int i; + char buf[25*3+1], *e; + + e = buf; + for(i = 0; i < n; i++){ + *e++ = ntab[reg[i] >> 4]; + *e++ = ntab[reg[i] & 0xf]; + *e++ = ' '; + } + *e++ = '\n'; + *e = 0; + dprint(buf); +} + +static void +dreg(char *s, Aport *p) +{ + dprint("%stask=%lux; cmd=%lux; ci=%lux; is=%lux\n", + s, p->task, p->cmd, p->ci, p->isr); +} + +static void +esleep(int ms) +{ + delay(ms); +} + +typedef struct { + Aport *p; + int i; +} Asleep; + +static int +ahciclear(void *v) +{ + Asleep *s; + + s = v; + return (s->p->ci & s->i) == 0; +} + +static void +aesleep(Aportm *, Asleep *a, int ms) +{ + ulong start; + + start = m->ticks; + while((a->p->ci & a->i) != 0) + if(TK2MS(m->ticks-start) >= ms) + break; +} + +static int +ahciwait(Aportc *c, int ms) +{ + Aport *p; + Asleep as; + + p = c->p; + p->ci = 1; + as.p = p; + as.i = 1; + aesleep(c->m, &as, ms); + if((p->task & 1) == 0 && p->ci == 0) + return 0; + dreg("ahciwait timeout ", c->p); + return -1; +} + +static int +setfeatures(Aportc *pc, uchar f) +{ + uchar *c; + Actab *t; + Alist *l; + + t = pc->m->ctab; + c = t->cfis; + + memset(c, 0, 0x20); + c[0] = 0x27; + c[1] = 0x80; + c[2] = 0xef; + c[3] = f; + c[7] = 0xa0; /* obsolete device bits */ + + l = pc->m->list; + l->flags = Lwrite|0x5; + l->len = 0; + l->ctab = PCIWADDR(t); + l->ctabhi = 0; + + return ahciwait(pc, 3*1000); +} + +static int +setudmamode(Aportc *pc, uchar f) +{ + uchar *c; + Actab *t; + Alist *l; + + t = pc->m->ctab; + c = t->cfis; + + memset(c, 0, 0x20); + c[0] = 0x27; + c[1] = 0x80; + c[2] = 0xef; + c[3] = 3; /* set transfer mode */ + c[7] = 0xa0; /* obsolete device bits */ + c[12] = 0x40 | f; /* sector count */ + + l = pc->m->list; + l->flags = Lwrite | 0x5; + l->len = 0; + l->ctab = PCIWADDR(t); + l->ctabhi = 0; + + return ahciwait(pc, 3*1000); +} + +static void +asleep(int ms) +{ + delay(ms); +} + +static int +ahciportreset(Aportc *c) +{ + ulong *cmd, i; + Aport *p; + + p = c->p; + cmd = &p->cmd; + *cmd &= ~(Afre|Ast); + for(i = 0; i < 500; i += 25){ + if((*cmd & Acr) == 0) + break; + asleep(25); + } + p->sctl = 1 | (p->sctl & ~7); + delay(1); + p->sctl &= ~7; + return 0; +} + +static ushort +gbit16(void *a) +{ + uchar *i; + + i = a; + return i[1]<<8 | i[0]; +} + +static ulong +gbit32(void *a) +{ + ulong j; + uchar *i; + + i = a; + j = i[3] << 24; + j |= i[2] << 16; + j |= i[1] << 8; + j |= i[0]; + return j; +} + +static uvlong +gbit64(void *a) +{ + uchar *i; + + i = a; + return (uvlong) gbit32(i+4)<<32 | gbit32(a); +} + +static int +ahciidentify0(Aportc *pc, void *id, int atapi) +{ + uchar *c; + Actab *t; + Alist *l; + Aprdt *p; + static uchar tab[] = { 0xec, 0xa1 }; + + t = pc->m->ctab; + c = t->cfis; + + memset(c, 0, 0x20); + c[0] = 0x27; + c[1] = 0x80; + c[2] = tab[atapi]; + c[7] = 0xa0; /* obsolete device bits */ + + l = pc->m->list; + l->flags = 1<<16 | 0x5; + l->len = 0; + l->ctab = PCIWADDR(t); + l->ctabhi = 0; + + memset(id, 0, 0x100); + p = &t->prdt; + p->dba = PCIWADDR(id); + p->dbahi = 0; + p->count = 1<<31 | (0x200-2) | 1; + + return ahciwait(pc, 3*1000); +} + +static vlong +ahciidentify(Aportc *pc, ushort *id) +{ + int i, sig; + vlong s; + Aportm *m; + + m = pc->m; + m->feat = 0; + m->smart = 0; + i = 0; + sig = pc->p->sig >> 16; + if(sig == 0xeb14){ + m->feat |= Datapi; + i = 1; + } + if(ahciidentify0(pc, id, i) == -1) + return -1; + + i = gbit16(id+83) | gbit16(id+86); + if(i & (1<<10)){ + m->feat |= Dllba; + s = gbit64(id+100); + }else + s = gbit32(id+60); + + if(m->feat & Datapi){ + i = gbit16(id+0); + if(i & 1) + m->feat |= Datapi16; + } + + i = gbit16(id+83); + if((i>>14) != 1) + return s; + if(i & (1<<3)) + m->feat |= Dpower; + i = gbit16(id+82); + if(i & 1) + m->feat |= Dsmart; + if(i & (1<<14)) + m->feat |= Dnop; + return s; +} + +static int +ahciquiet(Aport *a) +{ + ulong *p, i; + + p = &a->cmd; + *p &= ~Ast; + for(i = 0; i < 500; i += 50){ + if((*p & Acr) == 0) + goto stop; + asleep(50); + } + return -1; +stop: + if((a->task & (ASdrq|ASbsy)) == 0){ + *p |= Ast; + return 0; + } + + *p |= Aclo; + for(i = 0; i < 500; i += 50){ + if((*p & Aclo) == 0) + goto stop1; + asleep(50); + } + return -1; +stop1: + /* extra check */ + dprint("clo clear %lx\n", a->task); + if(a->task & ASbsy) + return -1; + *p |= Ast; + return 0; +} + +static int +ahciidle(Aport *port) +{ + ulong *p, i, r; + + p = &port->cmd; + if((*p & Arun) == 0) + return 0; + *p &= ~Ast; + r = 0; + for(i = 0; i < 500; i += 25){ + if((*p & Acr) == 0) + goto stop; + asleep(25); + } + r = -1; +stop: + if((*p & Afre) == 0) + return r; + *p &= ~Afre; + for(i = 0; i < 500; i += 25){ + if((*p & Afre) == 0) + return 0; + asleep(25); + } + return -1; +} + +/* + * §6.2.2.1 first part; comreset handled by reset disk. + * - remainder is handled by configdisk. + * - ahcirecover is a quick recovery from a failed command. + */ +int +ahciswreset(Aportc *pc) +{ + int i; + + i = ahciidle(pc->p); + pc->p->cmd |= Afre; + if(i == -1) + return -1; + if(pc->p->task & (ASdrq|ASbsy)) + return -1; + return 0; +} + +int +ahcirecover(Aportc *pc) +{ + ahciswreset(pc); + pc->p->cmd |= Ast; + if(setudmamode(pc, 5) == -1) + return -1; + return 0; +} + +static void* +malign(int size, int align) +{ + void *v; + + v = xspanalloc(size, align, 0); + memset(v, 0, size); + return v; +} + +static void +setupfis(Afis *f) +{ + f->base = malign(0x100, 0x100); + f->d = f->base + 0; + f->p = f->base + 0x20; + f->r = f->base + 0x40; + f->u = f->base + 0x60; + f->devicebits = (ulong*)(f->base + 0x58); +} + +static void +ahciwakeup(Aport *p) +{ + ushort s; + + s = p->sstatus; + if((s & 0x700) != 0x600) + return; + if((s & 7) != 1){ + print("ahci: slumbering drive unwakeable %ux\n", s); + return; + } + p->sctl = 3*Aipm | 0*Aspd | Adet; + delay(1); + p->sctl &= ~7; +// iprint("ahci: wake %ux -> %ux\n", s, p->sstatus); +} + +static int +ahciconfigdrive(Ahba *h, Aportc *c, int mode) +{ + Aportm *m; + Aport *p; + + p = c->p; + m = c->m; + + if(m->list == 0){ + setupfis(&m->fis); + m->list = malign(sizeof *m->list, 1024); + m->ctab = malign(sizeof *m->ctab, 128); + } + + if(p->sstatus & 3 && h->cap & Hsss){ + dprint("configdrive: spinning up ... [%lux]\n", p->sstatus); + p->cmd |= Apod|Asud; + asleep(1400); + } + + p->serror = SerrAll; + + p->list = PCIWADDR(m->list); + p->listhi = 0; + p->fis = PCIWADDR(m->fis.base); + p->fishi = 0; + p->cmd |= Afre | Ast; + + if((p->sstatus & 0x707) == 0x601) /* drive coming up in slumbering? */ + ahciwakeup(p); + + /* disable power managment sequence from book. */ + p->sctl = (3*Aipm) | (mode*Aspd) | (0*Adet); + p->cmd &= ~Aalpe; + + p->ie = IEM; + + return 0; +} + +static int +ahcienable(Ahba *h) +{ + h->ghc |= Hie; + return 0; +} + +static int +ahcidisable(Ahba *h) +{ + h->ghc &= ~Hie; + return 0; +} + +static int +countbits(ulong u) +{ + int i, n; + + n = 0; + for(i = 0; i < 32; i++) + if(u & (1<<i)) + n++; + return n; +} + +static int +ahciconf(Ctlr *c) +{ + ulong u; + Ahba *h; + static int count; + + h = c->hba = (Ahba*)c->mmio; + u = h->cap; + + if((u & Hsam) == 0) + h->ghc |= Hae; + + print("ahci%d port %#p: hba sss %ld; ncs %ld; coal %ld; mports %ld; " + "led %ld; clo %ld; ems %ld;\n", count++, h, + (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1, + (u>>24) & 1, (u>>6) & 1); + return countbits(h->pi); +} + +static int +ahcihbareset(Ahba *h) +{ + int wait; + + h->ghc |= 1; + for(wait = 0; wait < 1000; wait += 100){ + if(h->ghc == 0) + return 0; + delay(100); + } + return -1; +} + +static void +idmove(char *p, ushort *a, int n) +{ + int i; + char *op, *e; + + op = p; + for(i = 0; i < n/2; i++){ + *p++ = a[i] >> 8; + *p++ = a[i]; + } + *p = 0; + while(p > op && *--p == ' ') + *p = 0; + e = p; + for (p = op; *p == ' '; p++) + ; + memmove(op, p, n - (e - p)); +} + +static int +identify(Drive *d) +{ + ushort *id; + vlong osectors, s; + uchar oserial[21]; + SDunit *u; + + id = d->info; + s = ahciidentify(&d->portc, id); + if(s == -1){ + d->state = Derror; + return -1; + } + osectors = d->sectors; + memmove(oserial, d->serial, sizeof d->serial); + + d->sectors = s; + d->smartrs = 0; + + idmove(d->serial, id+10, 20); + idmove(d->firmware, id+23, 8); + idmove(d->model, id+27, 40); + + u = d->unit; + memset(u->inquiry, 0, sizeof u->inquiry); + u->inquiry[2] = 2; + u->inquiry[3] = 2; + u->inquiry[4] = sizeof u->inquiry - 4; + memmove(u->inquiry+8, d->model, 40); + + if((osectors == 0 || osectors != s) && + memcmp(oserial, d->serial, sizeof oserial) != 0){ + d->mediachange = 1; + u->sectors = 0; + } + + return 0; +} + +static void +clearci(Aport *p) +{ + if((p->cmd & Ast) == 0) + return; + p->cmd &= ~Ast; + p->cmd |= Ast; +} + +static void +updatedrive(Drive *d) +{ + ulong cause, serr, s0, pr, ewake; + char *name; + Aport *p; + static ulong last; + + pr = 1; + ewake = 0; + p = d->port; + cause = p->isr; + serr = p->serror; + p->isr = cause; + name = "??"; + if(d->unit && d->unit->name) + name = d->unit->name; + + if(p->ci == 0){ + d->portm.flag |= Fdone; + pr = 0; + }else if(cause & Adps) + pr = 0; + if(cause&Ifatal){ + ewake = 1; + dprint("Fatal\n"); + } + if(cause & Adhrs){ + if(p->task & (32|1)){ + dprint("Adhrs cause = %lux; serr = %lux; task=%lux\n", + cause, serr, p->task); + d->portm.flag |= Ferror; + ewake = 1; + } + pr = 0; + } + + if(pr) + dprint("%s: upd %lux ta %lux\n", name, cause, p->task); + if(cause & (Aprcs|Aifs)){ + s0 = d->state; + switch(p->sstatus & 7){ + case 0: + d->state = Dmissing; + break; + case 1: + if((p->sstatus & 0x700) == 0x600) + d->state = Dnew; + else + d->state = Derror; + break; + case 3: + /* power mgnt crap for surprise removal */ + p->ie |= Aprcs | Apcs; /* is this required? */ + d->state = Dreset; + break; + case 4: + d->state = Doffline; + break; + } + dprint("%s: %s → %s [Apcrs] %lux\n", name, diskstates[s0], + diskstates[d->state], p->sstatus); + if(s0 == Dready && d->state != Dready) + idprint("%s: pulled\n", name); + if(d->state != Dready) + d->portm.flag |= Ferror; + ewake = 1; + } + p->serror = serr; + if(ewake) + clearci(p); + last = cause; +} + +static void +pstatus(Drive *d, ulong s) +{ + /* + * bogus code because the first interrupt is currently dropped. + * likely my fault. serror may be cleared at the wrong time. + */ + switch(s){ + case 0: + d->state = Dmissing; + break; + case 2: /* should this be missing? need testcase. */ + dprint("pstatus 2\n"); + case 3: + d->wait = 0; + d->state = Dnew; + break; + case 4: + d->state = Doffline; + break; + case 6: + d->state = Dnew; + break; + } +} + +static int +configdrive(Drive *d) +{ + if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1) + return -1; + ilock(d); + pstatus(d, d->port->sstatus & 7); + iunlock(d); + return 0; +} + +static void +resetdisk(Drive *d) +{ + uint state, det, stat; + Aport *p; + + p = d->port; + det = p->sctl & 7; + stat = p->sstatus & 7; + state = (p->cmd>>28) & 0xf; + dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat); + if(stat != 3){ + ilock(d); + d->state = Dportreset; + iunlock(d); + return; + } + ilock(d); + state = d->state; + if(d->state != Dready || d->state != Dnew) + d->portm.flag |= Ferror; + clearci(p); /* satisfy sleep condition. */ + iunlock(d); + + qlock(&d->portm); + + if(p->cmd & Ast && ahciswreset(&d->portc) == -1){ + ilock(d); + d->state = Dportreset; /* get a bigger stick. */ + iunlock(d); + } else { + ilock(d); + d->state = Dmissing; + iunlock(d); + + configdrive(d); + } + dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]); + qunlock(&d->portm); +} + +static int +newdrive(Drive *d) +{ + char *name, *s; + Aportc *c; + Aportm *m; + + c = &d->portc; + m = &d->portm; + + name = d->unit->name; + if(name == 0) + name = "??"; + + if(d->port->task == 0x80) + return -1; + qlock(c->m); + if(setudmamode(c, 5) == -1){ + dprint("%s: can't set udma mode\n", name); + goto lose; + } + if(identify(d) == -1){ + dprint("%s: identify failure\n", name); + goto lose; + } + if(m->feat & Dpower && setfeatures(c, 0x85) == -1){ + m->feat &= ~Dpower; + if(ahcirecover(c) == -1) { + dprint("%s: ahcirecover failed\n", name); + goto lose; + } + } + + ilock(d); + d->state = Dready; + iunlock(d); + + qunlock(c->m); + + s = ""; + if(m->feat & Dllba) + s = "L"; + idprint("%s: %sLBA %lld sectors\n", d->unit->name, s, d->sectors); + idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial, + d->mediachange? "[mediachange]": ""); + + return 0; + +lose: + qunlock(&d->portm); + return -1; +} + +enum { + Nms = 256, + Mphywait = 2*1024/Nms - 1, + Midwait = 16*1024/Nms - 1, + Mcomrwait = 64*1024/Nms - 1, +}; + +static void +westerndigitalhung(Drive *d) +{ + if((d->portm.feat & Datapi) == 0 && d->active && + TK2MS(m->ticks - d->intick) > 5000){ + dprint("%s: drive hung; resetting [%lux] ci=%lx\n", + d->unit->name, d->port->task, d->port->ci); + d->state = Dreset; + } +} + +static ushort olds[NCtlr*NCtlrdrv]; + +static int +doportreset(Drive *d) +{ + int i; + + i = -1; + qlock(&d->portm); + if(ahciportreset(&d->portc) == -1) + dprint("ahciportreset fails\n"); + else + i = 0; + qunlock(&d->portm); + dprint("portreset → %s [task %lux]\n", diskstates[d->state], + d->port->task); + return i; +} + +static void +checkdrive(Drive *d, int i) +{ + ushort s; + char *name; + + ilock(d); + name = d->unit->name; + s = d->port->sstatus; + if(s != olds[i]){ + dprint("%s: status: %#ux -> %#ux: %s\n", name, olds[i], + s, diskstates[d->state]); + olds[i] = s; + d->wait = 0; + } + westerndigitalhung(d); + switch(d->state){ + case Dnull: + break; + case Dmissing: + case Dnew: + switch(s & 0x107){ + case 1: + ahciwakeup(d->port); + case 0: + break; + default: + dprint("%s: unknown status %04ux\n", name, s); + case 0x100: + if(++d->wait&Mphywait) + break; +reset: + if(++d->mode > DMsataii) + d->mode = 0; + if(d->mode == DMsatai){ /* we tried everything */ + d->state = Dportreset; + goto portreset; + } + dprint("%s: reset; new mode %s\n", name, + modename[d->mode]); + iunlock(d); + resetdisk(d); + ilock(d); + break; + case 0x103: + if((++d->wait&Midwait) == 0){ + dprint("%s: slow reset %#ux task=%#lux; %d\n", + name, s, d->port->task, d->wait); + goto reset; + } + s = d->port->task&0xff; + if(s == 0x7f || ((d->port->sig>>16) != 0xeb14 && + (s & ~0x17) != (1<<6))) + break; + iunlock(d); + newdrive(d); + ilock(d); + break; + } + break; + case Doffline: + if(d->wait++ & Mcomrwait) + break; + case Derror: + case Dreset: + dprint("%s: reset [%s]: mode %d; status %#ux\n", + name, diskstates[d->state], d->mode, s); + iunlock(d); + resetdisk(d); + ilock(d); + break; + case Dportreset: +portreset: + if(d->wait++ & 0xff && (s & 0x100) == 0) + break; + dprint("%s: portreset [%s]: mode %d; status %04ux\n", + name, diskstates[d->state], d->mode, s); + d->portm.flag |= Ferror; + clearci(d->port); + if((s & 7) == 0){ + d->state = Dmissing; + break; + } + iunlock(d); + doportreset(d); + ilock(d); + break; + } + iunlock(d); +} + +static void +iainterrupt(Ureg*, void *a) +{ + int i; + ulong cause, m; + Ctlr *c; + Drive *d; + + c = a; + ilock(c); + /* check drive here! */ + cause = c->hba->isr; + for(i = 0; i < c->ndrive; i++){ + m = 1 << i; + if((cause & m) == 0) + continue; + d = c->rawdrive + i; + ilock(d); + if(d->port->isr && c->hba->pi & m) + updatedrive(d); + c->hba->isr = m; + iunlock(d); + } + iunlock(c); +} + +static int +iaverify(SDunit *u) +{ + int i; + Ctlr *c; + Drive *d; + + c = u->dev->ctlr; + d = c->drive[u->subno]; + ilock(c); + ilock(d); + d->unit = u; + iunlock(d); + iunlock(c); + for(i = 0; i < 10; i++){ + checkdrive(d, d->driveno); + switch(d->state){ + case Dmissing: + if(i < 4 || d->port->sstatus & 0x733) + break; + /* fall through */ + case Dnull: + case Dready: + case Doffline: + print("sdiahci: drive %d in state %s after %d resets\n", + d->driveno, diskstates[d->state], i); + return 1; + } + delay(100); + } + print("sdiahci: drive %d won't come up; in state %s after %d resets\n", + d->driveno, diskstates[d->state], i); + return 1; +} + +static int +iaenable(SDev *s) +{ + Ctlr *c; + + c = s->ctlr; + ilock(c); + if(!c->enabled) { + if(c->ndrive == 0) + panic("iaenable: zero s->ctlr->ndrive"); + pcisetbme(c->pci); + setvec(c->pci->intl+VectorPIC, iainterrupt, c); + /* supposed to squelch leftover interrupts here. */ + ahcienable(c->hba); + c->enabled = 1; + } + iunlock(c); + return 1; +} + +static int +iadisable(SDev *s) +{ + Ctlr *c; + + c = s->ctlr; + ilock(c); + ahcidisable(c->hba); +// intrdisable(c->irq, iainterrupt, c, c->tbdf, name); + c->enabled = 0; + iunlock(c); + return 1; +} + +static int +iaonline(SDunit *unit) +{ + int r; + Ctlr *c; + Drive *d; + + c = unit->dev->ctlr; + d = c->drive[unit->subno]; + r = 0; + + if(d->portm.feat & Datapi && d->mediachange){ + r = scsionline(unit); + if(r > 0) + d->mediachange = 0; + return r; + } + + ilock(d); + if(d->mediachange){ + r = 2; + d->mediachange = 0; + /* devsd resets this after online is called; why? */ + unit->sectors = d->sectors; + unit->secsize = 512; + } else if(d->state == Dready) + r = 1; + iunlock(d); + return r; +} + +/* returns locked list! */ +static Alist* +ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba) +{ + uchar *c, acmd, dir, llba; + Alist *l; + Actab *t; + Aprdt *p; + static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35 }; + + dir = *cmd != 0x28; + llba = m->feat & Dllba? 1: 0; + acmd = tab[dir][llba]; + qlock(m); + l = m->list; + t = m->ctab; + c = t->cfis; + + c[0] = 0x27; + c[1] = 0x80; + c[2] = acmd; + c[3] = 0; + + c[4] = lba; /* sector lba low 7:0 */ + c[5] = lba >> 8; /* cylinder low lba mid 15:8 */ + c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */ + c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */ + if(llba == 0) + c[7] |= (lba>>24) & 7; + + c[8] = lba >> 24; /* sector (exp) lba 31:24 */ + c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */ + c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */ + c[11] = 0; /* features (exp); */ + + c[12] = n; /* sector count */ + c[13] = n >> 8; /* sector count (exp) */ + c[14] = 0; /* r */ + c[15] = 0; /* control */ + + *(ulong*)(c+16) = 0; + + l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */ + if(dir == Write) + l->flags |= Lwrite; + l->len = 0; + l->ctab = PCIWADDR(t); + l->ctabhi = 0; + + p = &t->prdt; + p->dba = PCIWADDR(data); + p->dbahi = 0; + p->count = 1<<31 | (512*n - 2) | 1; + + return l; +} + +static Alist* +ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n) +{ + int fill, len; + uchar *c; + Actab *t; + Alist *l; + Aprdt *p; + + qlock(m); + l = m->list; + t = m->ctab; + c = t->cfis; + + fill = m->feat & Datapi16? 16: 12; + if((len = r->clen) > fill) + len = fill; + memmove(t->atapi, r->cmd, len); + memset(t->atapi + len, 0, fill - len); + + c[0] = 0x27; + c[1] = 0x80; + c[2] = 0xa0; + if(n != 0) + c[3] = 1; /* dma */ + else + c[3] = 0; /* features (exp); */ + + c[4] = 0; /* sector lba low 7:0 */ + c[5] = n; /* cylinder low lba mid 15:8 */ + c[6] = n >> 8; /* cylinder hi lba hi 23:16 */ + c[7] = 0xa0; /* obsolete device bits */ + + *(ulong*)(c+8) = 0; + *(ulong*)(c+12) = 0; + *(ulong*)(c+16) = 0; + + l->flags = 1<<16 | Lpref | Latapi | 0x5; + if(r->write != 0 && data) + l->flags |= Lwrite; + l->len = 0; + l->ctab = PCIWADDR(t); + l->ctabhi = 0; + + if(data == 0) + return l; + + p = &t->prdt; + p->dba = PCIWADDR(data); + p->dbahi = 0; + p->count = 1<<31 | (n - 2) | 1; + + return l; +} + +static int +waitready(Drive *d) +{ + ulong s, t, i; + + for(i = 0; i < 120; i++){ + ilock(d); + s = d->port->sstatus; + t = d->port->task; + iunlock(d); + if((s & 0x100) == 0) + return -1; + if(d->state == Dready && (s & 7) == 3) + return 0; + if((i + 1) % 30 == 0) + print("%s: waitready: [%s] task=%lux sstat=%lux\n", + d->unit->name, diskstates[d->state], t, s); + esleep(1000); + } + print("%s: not responding; offline\n", d->unit->name); + ilock(d); + d->state = Doffline; + iunlock(d); + return -1; +} + +static int +iariopkt(SDreq *r, Drive *d) +{ + int n, count, try, max, flag, task; + char *name; + uchar *cmd, *data; + Aport *p; + Asleep as; + + cmd = r->cmd; + name = d->unit->name; + p = d->port; + + aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write], + r->dlen, r->data); +// if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f) +// return sdmodesense(r, cmd, d->info, sizeof d->info); + r->rlen = 0; + count = r->dlen; + max = 65536; + + try = 0; +retry: + if(waitready(d) == -1) + return SDeio; + data = r->data; + n = count; + if(n > max) + n = max; + d->active++; + ahcibuildpkt(&d->portm, r, data, n); + ilock(d); + d->portm.flag = 0; + iunlock(d); + p->ci = 1; + + as.p = p; + as.i = 1; + d->intick = m->ticks; + + while(ahciclear(&as) == 0) + ; + + ilock(d); + flag = d->portm.flag; + task = d->port->task; + iunlock(d); + + if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){ + d->port->ci = 0; /* @? */ + ahcirecover(&d->portc); + task = d->port->task; + } + d->active--; + qunlock(&d->portm); + if(flag == 0){ + if(++try == 10){ + print("%s: bad disk\n", name); + r->status = SDcheck; + return SDcheck; + } + print("%s: retry\n", name); + esleep(1000); + goto retry; + } + if(flag & Ferror){ + if((task & Eidnf) == 0) + print("%s: i/o error %ux\n", name, task); + r->status = SDcheck; + return SDcheck; + } + + data += n; + + r->rlen = data - (uchar*)r->data; + r->status = SDok; + return SDok; +} + +static int +iario(SDreq *r) +{ + int n, count, max, flag, task; + vlong lba; + char *name; + uchar *cmd, *data; + Aport *p; + Asleep as; + Ctlr *c; + Drive *d; + SDunit *unit; + + unit = r->unit; + c = unit->dev->ctlr; + d = c->drive[unit->subno]; + if(d->portm.feat & Datapi) + return iariopkt(r, d); + cmd = r->cmd; + name = d->unit->name; + p = d->port; + +// if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){ +// r->status = i; +// return i; +// } + + if(*cmd != 0x28 && *cmd != 0x2a){ + print("%s: bad cmd 0x%.2ux\n", name, cmd[0]); + r->status = SDcheck; + return SDcheck; + } + + lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5]; + count = cmd[7]<<8 | cmd[8]; + if(r->data == nil) + return SDok; + if(r->dlen < count * unit->secsize) + count = r->dlen / unit->secsize; + max = 128; + + if(waitready(d) == -1) + return SDeio; + data = r->data; + while(count > 0){ + n = count; + if(n > max) + n = max; + d->active++; + ahcibuild(&d->portm, cmd, data, n, lba); + ilock(d); + d->portm.flag = 0; + iunlock(d); + p->ci = 1; + + as.p = p; + as.i = 1; + d->intick = m->ticks; + + while(ahciclear(&as) == 0) + ; + + ilock(d); + flag = d->portm.flag; + task = d->port->task; + iunlock(d); + + if(task & (Efatal<<8) || + task & (ASbsy|ASdrq) && d->state == Dready){ + d->port->ci = 0; /* @? */ + ahcirecover(&d->portc); + task = d->port->task; + } + d->active--; + qunlock(&d->portm); + if(flag == 0 || flag & Ferror){ + print("%s: i/o error %ux @%lld\n", name, task, lba); + r->status = SDeio; + return SDeio; + } + + count -= n; + lba += n; + data += n * unit->secsize; + } + r->rlen = data - (uchar*)r->data; + r->status = SDok; + return SDok; +} + +/* + * configure drives 0-5 as ahci sata (c.f. errata) + */ +static int +iaahcimode(Pcidev *p) +{ + dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91), + pcicfgr8(p, 92), pcicfgr8(p, 93)); + pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */ +// pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */ + return 0; +} + +static void +iasetupahci(Ctlr *c) +{ + /* disable cmd block decoding. */ + pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15)); + pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15)); + + c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */ + c->lmmio[0xc/4] = (1<<6) - 1; /* five ports (supposedly ro pi reg) */ + + /* enable ahci mode; from ich9 datasheet */ + pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5); +} + +static SDev* +iapnp(void) +{ + int i, n, nunit, type; + ulong io; + Ctlr *c; + Drive *d; + Pcidev *p; + SDev *head, *tail, *s; + static int done; + + if (done || getconf("*noahciload") != nil) + return nil; + done = 1; + p = nil; + head = tail = nil; +loop: + while((p = pcimatch(p, 0, 0)) != nil){ + if(p->vid == 0x8086 && (p->did & 0xfffc) == 0x2680) + type = Tesb; + else if(p->vid == 0x8086 && p->did == 0x27c5) + type = Tich; /* 82801g[bh]m; compat mode fails */ + else if(p->vid == 0x8086 && (p->did & 0xfeff) == 0x2829) + type = Tich; /* ich8 */ + else if(p->vid == 0x8086 && (p->did & 0xfffe) == 0x2922) + type = Tich; /* ich8 */ + else if(p->vid == 0x1002 && p->did == 0x4380) + type = Tsb600; + else + continue; + if(niactlr == NCtlr){ + print("iapnp: %s: too many controllers\n", tname[type]); + break; + } + c = iactlr + niactlr; + s = sdevs + niactlr; + memset(c, 0, sizeof *c); + memset(s, 0, sizeof *s); + c->pci = p; + c->type = type; + io = p->mem[Abar].bar & ~0xf; + io = upamalloc(io, p->mem[Abar].size, 0); + if(io == 0){ + print("%s: address %#lux in use, did %#ux\n", + tname[c->type], io, p->did); + continue; + } + /* ugly hack: get this in compatibility mode; see memory.c:271 */ + if(io == 0x40000000) { + print("%s: did %#ux is in non-sata mode. bar %#lux\n", + tname[c->type], p->did, p->mem[Abar].bar); + continue; + } + c->mmio = KADDR(io); + c->lmmio = (ulong*)c->mmio; + if(Intel(c->type) && p->did != 0x2681) + iasetupahci(c); + nunit = ahciconf(c); +// ahcihbareset((Ahba*)c->mmio); + if(Intel(c->type) && iaahcimode(p) == -1) + break; + if(nunit < 1){ +// vunmap(c->mmio, p->mem[Abar].size); + continue; + } + niactlr++; + i = (c->hba->cap>>21) & 1; + print("%s: sata-%s with %d ports\n", tname[c->type], + "I\0II"+i*2, nunit); + s->ifc = &sdiahciifc; + s->ctlr = c; + s->nunit = nunit; + s->idno = 'E'; + c->sdev = s; + c->ndrive = nunit; + + /* map the drives -- they don't all need to be enabled. */ + memset(c->rawdrive, 0, sizeof c->rawdrive); + n = 0; + for(i = 0; i < NCtlrdrv; i++) { + d = c->rawdrive+i; + d->portno = i; + d->driveno = -1; + d->sectors = 0; + d->ctlr = c; + if((c->hba->pi & (1<<i)) == 0) + continue; +// d->state = Dnew; + d->port = (Aport*)(c->mmio + 0x80*i + 0x100); + d->portc.p = d->port; + d->portc.m = &d->portm; + d->driveno = n++; + c->drive[d->driveno] = d; + } + for(i = 0; i < n; i++) + if(ahciidle(c->drive[i]->port) == -1){ + print("%s: port %d wedged; abort\n", + tname[c->type], i); + goto loop; + } + for(i = 0; i < n; i++){ + c->drive[i]->mode = DMsatai; + configdrive(c->drive[i]); + } + + if(head) + tail->next = s; + else + head = s; + tail = s; + } + return head; +} + +static SDev* +iaid(SDev* sdev) +{ + int i; + Ctlr *c; + + for(; sdev; sdev = sdev->next){ + if(sdev->ifc != &sdiahciifc) + continue; + c = sdev->ctlr; + for(i = 0; i < NCtlr; i++) + if(c == iactlr + i) + sdev->idno = 'E' + i; + } + return nil; +} + +SDifc sdiahciifc = { + "iahci", + + iapnp, + nil, /* legacy */ + iaid, + iaenable, + iadisable, + + iaverify, + iaonline, + iario, + nil, + nil, + + scsibio, +}; diff --git a/os/boot/pc/sdmylex.c b/os/boot/pc/sdmylex.c index bca23489..d93077f1 100644 --- a/os/boot/pc/sdmylex.c +++ b/os/boot/pc/sdmylex.c @@ -26,8 +26,6 @@ typedef struct QLock{ int r; } QLock; typedef struct Rendez{ int r; } Rendez; #define intrenable(irq, f, c, tbdf, name) setvec(VectorPIC+(irq), f, c);\ USED(tbdf); -#define ioalloc(p, b, c, d) (1) -#define iofree(p) #define K2BPA(va, tbdf) PADDR(va) #define BPA2K(pa, tbdf) KADDR(pa) @@ -901,7 +899,7 @@ buggery: * PCI and VLB buses. */ cmd[0] = Ciesi; - cmd[1] = 4; + cmd[1] = 14; clen = 2; dlen = 256; if(issue(ctlr, cmd, clen, data, dlen)){ diff --git a/os/boot/pc/sdscsi.c b/os/boot/pc/sdscsi.c index ff8668fe..c39bbcd0 100644 --- a/os/boot/pc/sdscsi.c +++ b/os/boot/pc/sdscsi.c @@ -133,7 +133,7 @@ scsirio(SDreq* r) // cgascreenputs("C", 1); switch(r->unit->dev->ifc->rio(r)){ default: - return -1; + break; case SDcheck: if(!(r->flags & SDvalidsense)) return -1; @@ -151,7 +151,7 @@ scsirio(SDreq* r) return 2; if(r->sense[12] == 0x29) return 2; - return -1; + break; case 0x02: /* not ready */ /* * If no medium present, bail out. @@ -166,9 +166,9 @@ scsirio(SDreq* r) scsitest(r); return 2; default: - return -1; + break; } - return -1; + break; case SDok: return 0; } diff --git a/os/boot/pc/trap.c b/os/boot/pc/trap.c index 503e03f4..e1030eec 100644 --- a/os/boot/pc/trap.c +++ b/os/boot/pc/trap.c @@ -182,7 +182,7 @@ trapinit(void) */ outb(Int0ctl, Icw1|0x01); /* ICW1 - edge triggered, master, ICW4 will be sent */ - outb(Int0aux, VectorPIC); /* ICW2 - interrupt vector offset */ + outb(Int0aux, VectorPIC); /* ICW2 - interrupt vector offset */ outb(Int0aux, 0x04); /* ICW3 - have slave on level 2 */ outb(Int0aux, 0x01); /* ICW4 - 8086 mode, not buffered */ @@ -194,7 +194,7 @@ trapinit(void) */ outb(Int1ctl, Icw1|0x01); /* ICW1 - edge triggered, master, ICW4 will be sent */ - outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */ + outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */ outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */ outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */ outb(Int1aux, int1mask); @@ -315,13 +315,14 @@ trap(Ureg *ur) } while(h); } +extern void realmode0(void); /* in l.s */ + +extern int realmodeintr; +extern Ureg realmoderegs; + void realmode(int intr, Ureg *ureg) { - extern void realmode0(void); /* in l.s */ - extern int realmodeintr; - extern Ureg realmoderegs; - realmoderegs = *ureg; realmodeintr = intr; trapdisable(); diff --git a/os/boot/pc/x16.h b/os/boot/pc/x16.h index 9c204328..9727a11e 100644 --- a/os/boot/pc/x16.h +++ b/os/boot/pc/x16.h @@ -147,7 +147,7 @@ #define PUSHI(i) BYTE $0x68; WORD $i; /* i -> --(rSP) */ #define POPA BYTE $0x61 #define POPR(r) BYTE $(0x58|r) /* (rSP++) -> r */ -#define POPS(rS) BYTE $$(0x07|((rS)<<3)) /* (rSP++) -> r */ +#define POPS(rS) BYTE $(0x07|((rS)<<3)) /* (rSP++) -> r */ #define NOP BYTE $0x90 /* nop */ #define LGDT(gdtptr) BYTE $0x0F; /* LGDT */ \ |