diff options
| author | Konstantin Kirik (snegovick) <snegovick@uprojects.org> | 2025-12-28 12:27:31 +0300 |
|---|---|---|
| committer | Konstantin Kirik (snegovick) <snegovick@uprojects.org> | 2025-12-28 12:27:31 +0300 |
| commit | 78ee7d5717807e6ac779293d0d3c78341de6130a (patch) | |
| tree | a43e3b0f61318ac45e6d907c7cc5bad2c6d7f497 /os/ipengine/tlb.s | |
| parent | bdaf46cf45bbb59261da245d548a179d95a42768 (diff) | |
Move existing boards into subdits split per arch
Diffstat (limited to 'os/ipengine/tlb.s')
| -rw-r--r-- | os/ipengine/tlb.s | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/os/ipengine/tlb.s b/os/ipengine/tlb.s deleted file mode 100644 index c7451823..00000000 --- a/os/ipengine/tlb.s +++ /dev/null @@ -1,21 +0,0 @@ -#include "mem.h" -#define MB (1024*1024) - -/* - * TLB prototype entries, loaded once-for-all at startup, - * remaining unchanged thereafter. - * Limit the table to at most 8 entries to ensure - * it works on the 823 (other 8xx processors allow up to 32 TLB entries). - */ -#define TLBE(epn,rpn,twc) WORD $(epn); WORD $(twc); WORD $(rpn) - -TEXT tlbtab(SB), $-4 - - /* epn, rpn, twc */ - TLBE(KZERO|PHYSDRAM|TLBVALID, PHYSDRAM|PTEWRITE|PTELPS|PTESH|PTEVALID, PTE8MB|PTEVALID) /* DRAM, 8M */ - TLBE(KZERO|(PHYSDRAM+8*MB)|TLBVALID, (PHYSDRAM+8*MB)|PTEWRITE|PTELPS|PTESH|PTEVALID, PTE8MB|PTEVALID) /* DRAM, 8M */ - TLBE(KZERO|PHYSIMM|TLBVALID, PHYSIMM|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE512K|PTEVALID) /* IMMR, 512K (includes FPGA control and clock synth) */ - TLBE(KZERO|PHYSFLASH|TLBVALID, PHYSFLASH|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE8MB|PTEWT|PTEVALID) /* Flash, 8M */ - TLBE(KZERO|FPGAMEM|TLBVALID, FPGAMEM|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE8MB|PTEG|PTEVALID) /* FPGA mem, 8M */ -TEXT tlbtabe(SB), $-4 - RETURN |