diff options
| author | Konstantin Kirik (snegovick) <snegovick@uprojects.org> | 2025-12-28 12:27:31 +0300 |
|---|---|---|
| committer | Konstantin Kirik (snegovick) <snegovick@uprojects.org> | 2025-12-28 12:27:31 +0300 |
| commit | 78ee7d5717807e6ac779293d0d3c78341de6130a (patch) | |
| tree | a43e3b0f61318ac45e6d907c7cc5bad2c6d7f497 /os/ipengine/archipe.h | |
| parent | bdaf46cf45bbb59261da245d548a179d95a42768 (diff) | |
Move existing boards into subdits split per arch
Diffstat (limited to 'os/ipengine/archipe.h')
| -rw-r--r-- | os/ipengine/archipe.h | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/os/ipengine/archipe.h b/os/ipengine/archipe.h deleted file mode 100644 index 575f7d8d..00000000 --- a/os/ipengine/archipe.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * values for Brightstar Engineering ipEngine - */ -enum { - /* CS assignment */ - BOOTCS = 0, /* flash */ - FPGACS = 1, /* 8Mb FPGA space */ - DRAMCS = 2, - FPGACONFCS = 3, /* FPGA config */ - CLOCKCS = 4, /* clock synth reg */ -}; - -enum { - /* port A pins */ - VCLK= SIBIT(5), - BCLK= SIBIT(4), - - /* port B */ - EnableVCLK= IBIT(30), - EnableEnet= IBIT(29), - EnableRS232= IBIT(28), - EnetFullDuplex= IBIT(16), - - /* port C */ - nCONFIG = SIBIT(13), /* FPGA configuration */ - USBFullSpeed= SIBIT(12), - PDN= SIBIT(5), /* ? seems to control power to FPGA subsystem? */ - EnetLoopback= SIBIT(4), - - /* nSTATUS is ip_b1, conf_done is ip_b0 in PIPR (hardware doc wrongly says ip_b2 and ip_b1) */ - -}; |
