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| author | Yaroslav Kolomiiets <yarikos@gmail.com> | 2017-02-27 17:23:28 +0200 |
|---|---|---|
| committer | Yaroslav Kolomiiets <yarikos@gmail.com> | 2017-02-27 17:23:28 +0200 |
| commit | 7ef44d652ae9e5e1f5b3465d73684e4a54de73c0 (patch) | |
| tree | 2c76cd7d21332631439d1dc60d87cb66fd47db34 /emu/AIX/segflush-power.c | |
| parent | fd29964f362afd85503d5f005122cedf030c6aa1 (diff) | |
add AIX/power port
Diffstat (limited to 'emu/AIX/segflush-power.c')
| -rw-r--r-- | emu/AIX/segflush-power.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/emu/AIX/segflush-power.c b/emu/AIX/segflush-power.c new file mode 100644 index 00000000..5029b0aa --- /dev/null +++ b/emu/AIX/segflush-power.c @@ -0,0 +1,33 @@ +#include <sys/types.h> + +#include "dat.h" + + +/* + * from geoff collyer's port + * invalidate instruction cache and write back data cache from a to a+n-1, + * at least. + */ +int +segflush(void *a, ulong n) +{ + ulong *p; + + // cache blocks are often eight words (32 bytes) long, sometimes 16 bytes. + // need to determine it dynamically? + for (p = (ulong *)((ulong)a & ~7UL); (char *)p < (char *)a + n; p++) + __asm__("dcbst 0,r0\n\t" // not dcbf, which writes back, then invalidates + "icbi 0,r0\n\t" + : // no output + : "ar" (p) + ); + __asm__("sync\n\t" + : // no output + : + ); + __asm__("isync\n\t" + : // no output + : + ); + return 0; +} |
