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authorValery Ushakov <uwe@stderr.spb.ru>2019-03-10 03:44:16 +0200
committerValery Ushakov <uwe@stderr.spb.ru>2019-03-10 03:44:16 +0200
commit594bd56378a3a707845dd8813881c427a3a8d16e (patch)
tree5f18116b77d615f40c50d449a332dafd21347c05 /emu/AIX/segflush-power.c
parent9b7850d511c2c910abfb42ece20650b97fba5a72 (diff)
parent55520626f59983d296c98c008af92f7c5c27bf5f (diff)
Merged default into NetBSD/pthreads
Diffstat (limited to 'emu/AIX/segflush-power.c')
-rw-r--r--emu/AIX/segflush-power.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/emu/AIX/segflush-power.c b/emu/AIX/segflush-power.c
new file mode 100644
index 00000000..5029b0aa
--- /dev/null
+++ b/emu/AIX/segflush-power.c
@@ -0,0 +1,33 @@
+#include <sys/types.h>
+
+#include "dat.h"
+
+
+/*
+ * from geoff collyer's port
+ * invalidate instruction cache and write back data cache from a to a+n-1,
+ * at least.
+ */
+int
+segflush(void *a, ulong n)
+{
+ ulong *p;
+
+ // cache blocks are often eight words (32 bytes) long, sometimes 16 bytes.
+ // need to determine it dynamically?
+ for (p = (ulong *)((ulong)a & ~7UL); (char *)p < (char *)a + n; p++)
+ __asm__("dcbst 0,r0\n\t" // not dcbf, which writes back, then invalidates
+ "icbi 0,r0\n\t"
+ : // no output
+ : "ar" (p)
+ );
+ __asm__("sync\n\t"
+ : // no output
+ :
+ );
+ __asm__("isync\n\t"
+ : // no output
+ :
+ );
+ return 0;
+}