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authorCharles Forsyth <charles.forsyth@gmail.com>2018-12-21 15:05:38 +0000
committerCharles Forsyth <charles.forsyth@gmail.com>2018-12-21 15:05:38 +0000
commit0195c4e25fc394097552c7f5ebf3085ec2d201f5 (patch)
treef67d1be5b8f66a11756be790f1e9371340b5be9e /emu/AIX/segflush-power.c
parent9765fcf68d2e5e39e39c100f798b9d00202e0d0a (diff)
parentb743441fb25b17bc7b81d3fb599b4ff5f149368b (diff)
Merged in yk/inferno-os/AIX-power (pull request #17)
AIX-power port Approved-by: Charles Forsyth <charles.forsyth@gmail.com>
Diffstat (limited to 'emu/AIX/segflush-power.c')
-rw-r--r--emu/AIX/segflush-power.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/emu/AIX/segflush-power.c b/emu/AIX/segflush-power.c
new file mode 100644
index 00000000..5029b0aa
--- /dev/null
+++ b/emu/AIX/segflush-power.c
@@ -0,0 +1,33 @@
+#include <sys/types.h>
+
+#include "dat.h"
+
+
+/*
+ * from geoff collyer's port
+ * invalidate instruction cache and write back data cache from a to a+n-1,
+ * at least.
+ */
+int
+segflush(void *a, ulong n)
+{
+ ulong *p;
+
+ // cache blocks are often eight words (32 bytes) long, sometimes 16 bytes.
+ // need to determine it dynamically?
+ for (p = (ulong *)((ulong)a & ~7UL); (char *)p < (char *)a + n; p++)
+ __asm__("dcbst 0,r0\n\t" // not dcbf, which writes back, then invalidates
+ "icbi 0,r0\n\t"
+ : // no output
+ : "ar" (p)
+ );
+ __asm__("sync\n\t"
+ : // no output
+ :
+ );
+ __asm__("isync\n\t"
+ : // no output
+ :
+ );
+ return 0;
+}