diff options
| author | Konstantin Kirik (snegovick) <snegovick@uprojects.org> | 2026-01-02 03:19:40 +0300 |
|---|---|---|
| committer | Konstantin Kirik (snegovick) <snegovick@uprojects.org> | 2026-01-02 03:19:40 +0300 |
| commit | a5bc382f7bde875c4e29ec3fe86453c4683167df (patch) | |
| tree | e9f4df6b5adc35f5349da1c4e27b31f99734bdc1 | |
| parent | 3895ff5cfe62a37a4eab8ecd7256dba8304a3502 (diff) | |
Add MPU driver for stm32f769
| -rw-r--r-- | os/drivers/memory/stm32f7_mpu.c | 63 | ||||
| -rw-r--r-- | os/drivers/memory/stm32f7_mpu.h | 9 |
2 files changed, 72 insertions, 0 deletions
diff --git a/os/drivers/memory/stm32f7_mpu.c b/os/drivers/memory/stm32f7_mpu.c new file mode 100644 index 00000000..dbca7027 --- /dev/null +++ b/os/drivers/memory/stm32f7_mpu.c @@ -0,0 +1,63 @@ +#include <stdint.h> +#include "stm32f7_mpu.h" +#include <drivers/include/device.h> +#include <arch/aarch32/stm32f7/stm32f769xx.h> +#include <arch/aarch32/core_cm7.h> + +static void __mpu_disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +static void __mpu_enable(uint32_t ctrl) +{ + /* Enable the MPU */ + MPU->CTRL = ctrl | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +int stm32f7_mpu_init(struct device *dev) { + dev->devptr = (void *)MPU; + + __mpu_disable(); + MPU->RNR = MPU_REGION_NUMBER0; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = 0; // Base addr + + uint32_t rasr = MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos; + rasr |= MPU_REGION_SIZE_4GB << MPU_RASR_SIZE_Pos; + rasr |= MPU_REGION_NO_ACCESS << MPU_RASR_AP_Pos; + rasr |= MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos; + rasr |= MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos; + rasr |= MPU_ACCESS_SHAREABLE << MPU_RASR_S_Pos; + rasr |= MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos; + rasr |= 0x87 << MPU_RASR_SRD_Pos; // Sub region disable + rasr |= MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos; + + MPU->RASR = rasr; + + __mpu_enable(MPU_PRIVILEGED_DEFAULT); + + return 0; +} + +int stm32f7_mpu_deinit(struct device *dev) { + return 0; +} diff --git a/os/drivers/memory/stm32f7_mpu.h b/os/drivers/memory/stm32f7_mpu.h new file mode 100644 index 00000000..4e81453c --- /dev/null +++ b/os/drivers/memory/stm32f7_mpu.h @@ -0,0 +1,9 @@ +#ifndef __STM32F7_MPU_H__ +#define __STM32F7_MPU_H__ + +#include <drivers/include/device.h> + +int stm32f7_mpu_init(struct device *dev); +int stm32f7_mpu_deinit(struct device *dev); + +#endif/*__STM32F7_MPU_H__*/ |
