Re-use CONFIG_definitions instead of cmsis ones

2 files changed, 10 insertions, 13 deletions

diff --git a/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c b/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c
index bf363777..695a9271 100644
--- a/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c
+++ b/os/arch/aarch32/armv7e_m/stm32f7/system_stm32f7xx.c
@@ -47,10 +47,6 @@
 #include <config.h>
 #include "stm32f7xx.h"
 
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
@@ -122,7 +118,7 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 16000000;
+  uint32_t SystemCoreClock = HSI_VALUE;
   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
   const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
 
@@ -211,7 +207,7 @@ void SystemCoreClockUpdate(void)
       SystemCoreClock = HSI_VALUE;
       break;
     case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
+      SystemCoreClock = CONFIG_BOARD_HSE_CLK;
       break;
     case 0x08:  /* PLL used as system clock source */
 
@@ -224,7 +220,7 @@ void SystemCoreClockUpdate(void)
       if (pllsource != 0)
       {
         /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+        pllvco = (CONFIG_BOARD_HSE_CLK / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
       }
       else
       {
@@ -233,7 +229,7 @@ void SystemCoreClockUpdate(void)
       }
 
       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
+      SystemCoreClock = pllvco / pllp;
       break;
     default:
       SystemCoreClock = HSI_VALUE;
diff --git a/os/drivers/clock/stm32f769_clock_control.c b/os/drivers/clock/stm32f769_clock_control.c
index 31cc8f1a..2b4c1fe1 100644
--- a/os/drivers/clock/stm32f769_clock_control.c
+++ b/os/drivers/clock/stm32f769_clock_control.c
@@ -9,7 +9,7 @@
 #include "stm32f769_clocks.h"
 
 #define STM32F769_CLOCK_ID_OFFSET(id) (((id) >> 6U) & 0xFFU)
-#define STM32F769_CLOCK_ID_BIT(id)   ((id)&0x1FU)
+#define STM32F769_CLOCK_ID_BIT(id)   (id & 0x1FU)
 
 volatile uint64_t uptime_ctr;
 
@@ -18,6 +18,8 @@ void SysTick_Handler(void) {
 }
 
 int stm32f769_clock_control_on(uint16_t id) {
+  uint32_t addr = RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id);
+  uint32_t bit = STM32F769_CLOCK_ID_BIT(id);
   sys_set_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id),
               STM32F769_CLOCK_ID_BIT(id));
   int ret = sys_test_bit(RCC_BASE + STM32F769_CLOCK_ID_OFFSET(id),
@@ -126,7 +128,6 @@ int stm32f769_clock_control_get_rate(uint16_t id, uint32_t *rate)
 int stm32f769_clock_control_init(struct device *dev)
 {
   uint32_t tickstart;
-  uint32_t pll_config;
 
   if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) {
     if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0)) {// && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) {
@@ -136,10 +137,10 @@ int stm32f769_clock_control_init(struct device *dev)
 
 #if defined(CONFIG_BOARD_HSE_CLK)
 #if CONFIG_BOARD_HSE_BYP == 1
-    sys_set_bit(RCC->CR, RCC_CR_HSEBYP);
-    sys_set_bit(RCC->CR, RCC_CR_HSEON);
+    RCC->CR |= RCC_CR_HSEBYP;
+    RCC->CR |= RCC_CR_HSEON;
 #else
-    sys_set_bit(RCC->CR, RCC_CR_HSEON);
+    RCC->CR |= RCC_CR_HSEON;
 #endif
     /* Get Start Tick*/
     tickstart = uptime_ctr;